HMAC Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	20.770s	5.972ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.030s	22.082us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.990s	61.105us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.570s	1.659ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.670s	597.973us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	34.755m	190.321ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.990s	61.105us	20	20	100.00
		hmac_csr_aliasing	9.670s	597.973us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.731m	14.071ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	58.140s	4.964ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	9.759m	91.882ms	50	50	100.00
		hmac_test_sha384_vectors	37.889m	718.987ms	49	50	98.00
		hmac_test_sha512_vectors	37.795m	212.608ms	48	50	96.00
		hmac_test_hmac_vectors	1.520s	365.640us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.471m	25.209ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	29.300m	4.961ms	50	50	100.00
V2	error	hmac_error	3.869m	37.277ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.724m	5.425ms	50	50	100.00
V2	save_and_restore	hmac_smoke	20.770s	5.972ms	50	50	100.00
		hmac_long_msg	2.731m	14.071ms	50	50	100.00
		hmac_back_pressure	58.140s	4.964ms	50	50	100.00
		hmac_datapath_stress	29.300m	4.961ms	50	50	100.00
		hmac_burst_wr	1.471m	25.209ms	50	50	100.00
		hmac_stress_all	1.005h	441.358ms	12	50	24.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	20.770s	5.972ms	50	50	100.00
		hmac_long_msg	2.731m	14.071ms	50	50	100.00
		hmac_back_pressure	58.140s	4.964ms	50	50	100.00
		hmac_datapath_stress	29.300m	4.961ms	50	50	100.00
		hmac_burst_wr	1.471m	25.209ms	50	50	100.00
		hmac_error	3.869m	37.277ms	50	50	100.00
		hmac_wipe_secret	1.724m	5.425ms	50	50	100.00
		hmac_test_sha256_vectors	9.759m	91.882ms	50	50	100.00
		hmac_test_sha384_vectors	37.889m	718.987ms	49	50	98.00
		hmac_test_sha512_vectors	37.795m	212.608ms	48	50	96.00
		hmac_test_hmac_vectors	1.520s	365.640us	50	50	100.00
		hmac_stress_all	1.005h	441.358ms	12	50	24.00
V2	stress_all	hmac_stress_all	1.005h	441.358ms	12	50	24.00
V2	alert_test	hmac_alert_test	0.650s	24.659us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	34.057us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.570s	1.009ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.570s	1.009ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.030s	22.082us	5	5	100.00
		hmac_csr_rw	0.990s	61.105us	20	20	100.00
		hmac_csr_aliasing	9.670s	597.973us	5	5	100.00
		hmac_same_csr_outstanding	2.550s	1.180ms	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.030s	22.082us	5	5	100.00
		hmac_csr_rw	0.990s	61.105us	20	20	100.00
		hmac_csr_aliasing	9.670s	597.973us	5	5	100.00
		hmac_same_csr_outstanding	2.550s	1.180ms	20	20	100.00
V2		TOTAL			649	690	94.06
V2S	tl_intg_err	hmac_sec_cm	1.020s	92.545us	5	5	100.00
		hmac_tl_intg_err	4.730s	461.390us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.730s	461.390us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	20.770s	5.972ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	19.662m	6.782ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			779	830	93.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.51	95.85	92.94	100.00	74.36	91.89	99.49	93.06

Failure Buckets

UVM_FATAL (hmac_test_vectors_sha_vseq.sv:28) virtual_sequencer [hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_*/SHA2_*/SHA2_* has 22 failures:

Test hmac_stress_all_with_rand_reset has 3 failures.

0.hmac_stress_all_with_rand_reset.37289515390582864634963528567112284097011483471274287178255488054908354529631
Line 74050, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 14972691219 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 14972691219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.hmac_stress_all_with_rand_reset.34480597806545670485085233498877607356265985455938268962734848015682074719321
Line 12870, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 63780342895 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 63780342895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test hmac_stress_all has 19 failures.

2.hmac_stress_all.110536532046015405482678928186942918073971665150802032645552496737522101225211
Line 44872, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log

  UVM_FATAL @ 49460743226 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 49460743226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.hmac_stress_all.65155149844677530600510159242557013655157937622830405866582571707288862227534
Line 85081, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all/latest/run.log

  UVM_FATAL @ 353348395377 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 353348395377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

UVM_FATAL (hmac_test_vectors_sha_vseq.sv:28) virtual_sequencer [hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_*/SHA2_*/SHA2_* has 21 failures:

Test hmac_stress_all has 19 failures.

0.hmac_stress_all.50949688067620910922245677916958985898157341294498948520355362483264394683853
Line 34204, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log

  UVM_FATAL @ 48708029526 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 48708029526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.hmac_stress_all.66922499638004563251394445067447568192957085303763549393907025292986220882103
Line 17221, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all/latest/run.log

  UVM_FATAL @ 3776210201 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 3776210201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

Test hmac_stress_all_with_rand_reset has 2 failures.

2.hmac_stress_all_with_rand_reset.41569378095606473460732902083035974980943203432262419568817639056344886451554
Line 37009, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 4717322416 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 4717322416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.hmac_stress_all_with_rand_reset.30588198234419342817576676956531169810128714202987967714842712145437625746312
Line 251, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   4352548 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @   4352548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test hmac_stress_all_with_rand_reset has 5 failures.
  - 1.hmac_stress_all_with_rand_reset.70313861026270459051825912994757905441448989494494641872440415262144381943145
    Line 108638, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6782462054 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6782462054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.hmac_stress_all_with_rand_reset.34006927863749921104256099525851589263755229975595070595636718590269739715995
    Line 7979, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2403248034 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2403248034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test hmac_test_sha512_vectors has 2 failures.
  - 26.hmac_test_sha512_vectors.14580205188140448224567151966744437867401336103369315893150742670544471791037
    Line 151900, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.hmac_test_sha512_vectors.38091389858488423483138788261868757258039612884063444429207384445467560260139
    Line 115399, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/37.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_test_sha384_vectors has 1 failures.
  - 40.hmac_test_sha384_vectors.19618980364335728459593882293651219375180296427885898982150964331862652683143
    Line 256670, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/40.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```