HMAC Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	31.240s	10.020ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.010s	155.412us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.950s	277.464us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.860s	2.701ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.790s	4.013ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.111m	150.460ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.950s	277.464us	20	20	100.00
		hmac_csr_aliasing	8.790s	4.013ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.626m	44.455ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	52.750s	6.577ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	9.412m	81.816ms	49	50	98.00
		hmac_test_sha384_vectors	38.025m	166.293ms	49	50	98.00
		hmac_test_sha512_vectors	37.300m	650.645ms	49	50	98.00
		hmac_test_hmac_vectors	1.510s	741.074us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.345m	5.841ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	25.156m	19.024ms	50	50	100.00
V2	error	hmac_error	2.994m	40.585ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.738m	14.760ms	50	50	100.00
V2	save_and_restore	hmac_smoke	31.240s	10.020ms	50	50	100.00
		hmac_long_msg	2.626m	44.455ms	50	50	100.00
		hmac_back_pressure	52.750s	6.577ms	50	50	100.00
		hmac_datapath_stress	25.156m	19.024ms	50	50	100.00
		hmac_burst_wr	1.345m	5.841ms	50	50	100.00
		hmac_stress_all	30.574m	490.398ms	8	50	16.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	31.240s	10.020ms	50	50	100.00
		hmac_long_msg	2.626m	44.455ms	50	50	100.00
		hmac_back_pressure	52.750s	6.577ms	50	50	100.00
		hmac_datapath_stress	25.156m	19.024ms	50	50	100.00
		hmac_burst_wr	1.345m	5.841ms	50	50	100.00
		hmac_error	2.994m	40.585ms	50	50	100.00
		hmac_wipe_secret	1.738m	14.760ms	50	50	100.00
		hmac_test_sha256_vectors	9.412m	81.816ms	49	50	98.00
		hmac_test_sha384_vectors	38.025m	166.293ms	49	50	98.00
		hmac_test_sha512_vectors	37.300m	650.645ms	49	50	98.00
		hmac_test_hmac_vectors	1.510s	741.074us	50	50	100.00
		hmac_stress_all	30.574m	490.398ms	8	50	16.00
V2	stress_all	hmac_stress_all	30.574m	490.398ms	8	50	16.00
V2	alert_test	hmac_alert_test	0.630s	12.119us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	19.776us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.410s	82.480us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.410s	82.480us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.010s	155.412us	5	5	100.00
		hmac_csr_rw	0.950s	277.464us	20	20	100.00
		hmac_csr_aliasing	8.790s	4.013ms	5	5	100.00
		hmac_same_csr_outstanding	2.430s	169.881us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.010s	155.412us	5	5	100.00
		hmac_csr_rw	0.950s	277.464us	20	20	100.00
		hmac_csr_aliasing	8.790s	4.013ms	5	5	100.00
		hmac_same_csr_outstanding	2.430s	169.881us	20	20	100.00
V2		TOTAL			645	690	93.48
V2S	tl_intg_err	hmac_sec_cm	1.040s	753.513us	5	5	100.00
		hmac_tl_intg_err	4.480s	270.615us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.480s	270.615us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	31.240s	10.020ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	19.716m	12.738ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			775	830	93.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	15	11	68.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.58	95.85	92.94	100.00	74.36	91.89	99.49	93.58

Failure Buckets

UVM_FATAL (hmac_test_vectors_sha_vseq.sv:28) virtual_sequencer [hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_*/SHA2_*/SHA2_* has 28 failures:

Test hmac_stress_all has 23 failures.

0.hmac_stress_all.95397502776326331094044565540686100544316473631153132384310924887437310518896
Line 249, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log

  UVM_FATAL @   1867397 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @   1867397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.hmac_stress_all.109122439067590212025122356867797674702841385589426307313505898521218869967668
Line 41328, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all/latest/run.log

  UVM_FATAL @ 5434836234 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 5434836234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 21 more failures.

Test hmac_stress_all_with_rand_reset has 5 failures.

2.hmac_stress_all_with_rand_reset.6661353268515817672987557839958605839499441580572246193548737071419201332543
Line 254, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  92553910 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @  92553910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.hmac_stress_all_with_rand_reset.75839944716717227405703216794192058888822614681136357413438849538322284547553
Line 5629, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 4027768213 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 4027768213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (hmac_test_vectors_sha_vseq.sv:28) virtual_sequencer [hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_*/SHA2_*/SHA2_* has 22 failures:

Test hmac_stress_all has 19 failures.

3.hmac_stress_all.30989760345684051289414020917651299879019688215108728517250834575098064413267
Line 35015, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log

  UVM_FATAL @ 9206060527 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 9206060527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.hmac_stress_all.41098937794717320044574425215311470503254858588417257874002215620299698794325
Line 249, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all/latest/run.log

  UVM_FATAL @  13076970 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @  13076970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

Test hmac_stress_all_with_rand_reset has 3 failures.

6.hmac_stress_all_with_rand_reset.34121563335016565945808373877919601239894938268354715998407193618532641440833
Line 87807, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 12737947038 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 12737947038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.hmac_stress_all_with_rand_reset.115182195851643044605854836236944216234814799636817844807625896818848169822996
Line 251, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   2012112 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @   2012112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test hmac_test_sha384_vectors has 1 failures.
  - 12.hmac_test_sha384_vectors.68517490318600676285925270810235257631125680274124160061457726473686647265912
    Line 236410, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/12.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_test_sha512_vectors has 1 failures.
  - 25.hmac_test_sha512_vectors.67879160428921719129551979342424911861557500604251138675525113605824060078778
    Line 218291, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/25.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_test_sha256_vectors has 1 failures.
  - 48.hmac_test_sha256_vectors.108295751351451603762338552250318704090862888973969143902295174159447394548786
    Line 69027, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/48.hmac_test_sha256_vectors/latest/run.log
```
  UVM_FATAL @ 800000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 800000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 800000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 0.hmac_stress_all_with_rand_reset.19028192661225696883425538754050174938655488778218978014158440870005196971918
    Line 102666, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33930942982 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33930942982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.19044664967089954895252797399816323522613487288560699144132037748762012766414
    Line 13246, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 896493608 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 896493608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```