HMAC Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	23.100s	4.372ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.030s	34.117us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.990s	29.661us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.850s	5.486ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.410s	2.335ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	5.114m	19.326ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.990s	29.661us	20	20	100.00
		hmac_csr_aliasing	9.410s	2.335ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.399m	100.090ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	58.570s	1.120ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	9.509m	88.821ms	50	50	100.00
		hmac_test_sha384_vectors	36.195m	168.771ms	46	50	92.00
		hmac_test_sha512_vectors	36.559m	328.422ms	46	50	92.00
		hmac_test_hmac_vectors	1.530s	90.349us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.390m	66.502ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	19.900m	3.362ms	50	50	100.00
V2	error	hmac_error	3.795m	17.407ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.074m	97.242ms	50	50	100.00
V2	save_and_restore	hmac_smoke	23.100s	4.372ms	50	50	100.00
		hmac_long_msg	2.399m	100.090ms	50	50	100.00
		hmac_back_pressure	58.570s	1.120ms	50	50	100.00
		hmac_datapath_stress	19.900m	3.362ms	50	50	100.00
		hmac_burst_wr	1.390m	66.502ms	50	50	100.00
		hmac_stress_all	1.487h	295.999ms	6	50	12.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	23.100s	4.372ms	50	50	100.00
		hmac_long_msg	2.399m	100.090ms	50	50	100.00
		hmac_back_pressure	58.570s	1.120ms	50	50	100.00
		hmac_datapath_stress	19.900m	3.362ms	50	50	100.00
		hmac_burst_wr	1.390m	66.502ms	50	50	100.00
		hmac_error	3.795m	17.407ms	50	50	100.00
		hmac_wipe_secret	2.074m	97.242ms	50	50	100.00
		hmac_test_sha256_vectors	9.509m	88.821ms	50	50	100.00
		hmac_test_sha384_vectors	36.195m	168.771ms	46	50	92.00
		hmac_test_sha512_vectors	36.559m	328.422ms	46	50	92.00
		hmac_test_hmac_vectors	1.530s	90.349us	50	50	100.00
		hmac_stress_all	1.487h	295.999ms	6	50	12.00
V2	stress_all	hmac_stress_all	1.487h	295.999ms	6	50	12.00
V2	alert_test	hmac_alert_test	0.650s	53.941us	50	50	100.00
V2	intr_test	hmac_intr_test	0.690s	28.250us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.330s	86.481us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.330s	86.481us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.030s	34.117us	5	5	100.00
		hmac_csr_rw	0.990s	29.661us	20	20	100.00
		hmac_csr_aliasing	9.410s	2.335ms	5	5	100.00
		hmac_same_csr_outstanding	2.600s	158.342us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.030s	34.117us	5	5	100.00
		hmac_csr_rw	0.990s	29.661us	20	20	100.00
		hmac_csr_aliasing	9.410s	2.335ms	5	5	100.00
		hmac_same_csr_outstanding	2.600s	158.342us	20	20	100.00
V2		TOTAL			638	690	92.46
V2S	tl_intg_err	hmac_sec_cm	1.060s	203.140us	5	5	100.00
		hmac_tl_intg_err	4.460s	323.996us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.460s	323.996us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	23.100s	4.372ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.412m	14.783ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			768	830	92.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.58	95.85	92.94	100.00	74.36	91.89	99.49	93.58

Failure Buckets

UVM_FATAL (hmac_test_vectors_sha_vseq.sv:28) virtual_sequencer [hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_*/SHA2_*/SHA2_*

has 29 failures:

Test hmac_stress_all has 25 failures.

0.hmac_stress_all.25196145300287185974806600916961979050548625075111676952916639677954436672031
Line 23240, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log

  UVM_FATAL @ 2333953081 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 2333953081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.hmac_stress_all.54832567588926493756655799360483983237362917793717250724924775573959422030322
Line 116967, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log

  UVM_FATAL @ 112732396807 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 112732396807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more failures.

Test hmac_stress_all_with_rand_reset has 4 failures.

0.hmac_stress_all_with_rand_reset.29275158130396667492883032015808973376627922301277020840341570749517658602116
Line 251, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   1590509 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @   1590509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.hmac_stress_all_with_rand_reset.112845442326678790571730515187561250481531343503193547984971293413563823450495
Line 75657, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 14783229532 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 14783229532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (hmac_test_vectors_sha_vseq.sv:28) virtual_sequencer [hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_*/SHA2_*/SHA2_*

has 22 failures:

Test hmac_stress_all_with_rand_reset has 3 failures.

1.hmac_stress_all_with_rand_reset.112261979439822643865491713427517249618473277268018695960147649720035603874221
Line 251, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   4321925 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @   4321925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.hmac_stress_all_with_rand_reset.96754310823453825612818115669037924356972070378269796838942694559007160607332
Line 251, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   2233150 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @   2233150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test hmac_stress_all has 19 failures.

3.hmac_stress_all.23903144875311119912946793299207122183755368096698618982080765908481807438492
Line 21091, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log

  UVM_FATAL @ 7938428610 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 7938428610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.hmac_stress_all.94208443877091915805256870631908194735315769661877747852062157229755435462865
Line 74595, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all/latest/run.log

  UVM_FATAL @ 51442241320 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 51442241320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 8 failures:
- Test hmac_test_sha384_vectors has 4 failures.
  - 1.hmac_test_sha384_vectors.112494697528739069922533845886025446932805584276437930509529826632964791834814
    Line 292805, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.hmac_test_sha384_vectors.14769342545238236052816871908763915254835650170236901978987664789755980831863
    Line 149713, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test hmac_test_sha512_vectors has 4 failures.
  - 9.hmac_test_sha512_vectors.1391011894336213153330425180534763571204120704906432298263496846762074951076
    Line 240796, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.hmac_test_sha512_vectors.75865113515332741102943413821264572295430392882756811804384701893856899274018
    Line 120484, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/23.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test hmac_stress_all_with_rand_reset has 3 failures.
  - 5.hmac_stress_all_with_rand_reset.111962381841357183436382060359405818400457518076370992956233243124042196506118
    Line 1663, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7710760347 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7710760347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.hmac_stress_all_with_rand_reset.40837581475202279204225854190522141587749693989620334642064416757248758293196
    Line 14802, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 74073339929 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 74073339929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.