HMAC Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	23.260s	7.382ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.060s	156.226us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	36.481us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	11.000s	957.770us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.060s	2.440ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.238m	57.552ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	36.481us	20	20	100.00
		hmac_csr_aliasing	9.060s	2.440ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.092m	48.809ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	59.970s	9.846ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	9.999m	230.773ms	50	50	100.00
		hmac_test_sha384_vectors	40.672m	369.647ms	48	50	96.00
		hmac_test_sha512_vectors	38.122m	174.742ms	48	50	96.00
		hmac_test_hmac_vectors	1.470s	73.189us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.245m	49.429ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	21.759m	4.455ms	50	50	100.00
V2	error	hmac_error	3.418m	109.557ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.593m	18.450ms	50	50	100.00
V2	save_and_restore	hmac_smoke	23.260s	7.382ms	50	50	100.00
		hmac_long_msg	3.092m	48.809ms	50	50	100.00
		hmac_back_pressure	59.970s	9.846ms	50	50	100.00
		hmac_datapath_stress	21.759m	4.455ms	50	50	100.00
		hmac_burst_wr	1.245m	49.429ms	50	50	100.00
		hmac_stress_all	49.188m	59.913ms	9	50	18.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	23.260s	7.382ms	50	50	100.00
		hmac_long_msg	3.092m	48.809ms	50	50	100.00
		hmac_back_pressure	59.970s	9.846ms	50	50	100.00
		hmac_datapath_stress	21.759m	4.455ms	50	50	100.00
		hmac_burst_wr	1.245m	49.429ms	50	50	100.00
		hmac_error	3.418m	109.557ms	50	50	100.00
		hmac_wipe_secret	1.593m	18.450ms	50	50	100.00
		hmac_test_sha256_vectors	9.999m	230.773ms	50	50	100.00
		hmac_test_sha384_vectors	40.672m	369.647ms	48	50	96.00
		hmac_test_sha512_vectors	38.122m	174.742ms	48	50	96.00
		hmac_test_hmac_vectors	1.470s	73.189us	50	50	100.00
		hmac_stress_all	49.188m	59.913ms	9	50	18.00
V2	stress_all	hmac_stress_all	49.188m	59.913ms	9	50	18.00
V2	alert_test	hmac_alert_test	0.640s	45.728us	50	50	100.00
V2	intr_test	hmac_intr_test	0.660s	29.341us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.280s	827.838us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.280s	827.838us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.060s	156.226us	5	5	100.00
		hmac_csr_rw	0.970s	36.481us	20	20	100.00
		hmac_csr_aliasing	9.060s	2.440ms	5	5	100.00
		hmac_same_csr_outstanding	2.600s	608.980us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.060s	156.226us	5	5	100.00
		hmac_csr_rw	0.970s	36.481us	20	20	100.00
		hmac_csr_aliasing	9.060s	2.440ms	5	5	100.00
		hmac_same_csr_outstanding	2.600s	608.980us	20	20	100.00
V2		TOTAL			645	690	93.48
V2S	tl_intg_err	hmac_sec_cm	0.880s	57.420us	5	5	100.00
		hmac_tl_intg_err	4.270s	914.145us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.270s	914.145us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	23.260s	7.382ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.497m	19.482ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			775	830	93.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	15	12	75.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.54	95.85	92.99	100.00	74.36	91.89	99.49	93.23

Failure Buckets

UVM_FATAL (hmac_test_vectors_sha_vseq.sv:28) virtual_sequencer [hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_*/SHA2_*/SHA2_* has 23 failures:

Test hmac_stress_all has 21 failures.

0.hmac_stress_all.69487400896826895985937900571450084633061223766269288675137010585144265430731
Line 1568, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log

  UVM_FATAL @ 1431758090 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 1431758090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.hmac_stress_all.68703916547205901952965554286811186002027292697303862771473768451176004916364
Line 124940, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all/latest/run.log

  UVM_FATAL @ 138031434610 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 138031434610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 19 more failures.

Test hmac_stress_all_with_rand_reset has 2 failures.

2.hmac_stress_all_with_rand_reset.26640009705999154156283597039722500255969438824123574270817500256598953455801
Line 1000, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 3518163777 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 3518163777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.hmac_stress_all_with_rand_reset.63147287894562068231913011727068652315247988786966256233878004188627422564522
Line 23741, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 7222777720 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 7222777720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (hmac_test_vectors_sha_vseq.sv:28) virtual_sequencer [hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_*/SHA2_*/SHA2_* has 22 failures:

Test hmac_stress_all has 20 failures.

2.hmac_stress_all.111835316944471786806831530179672049588638103622692061355549235094229759194777
Line 249, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log

  UVM_FATAL @   1436239 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @   1436239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.hmac_stress_all.75125839435388062408356260752628743479685836976286793521804918180847741205123
Line 93461, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all/latest/run.log

  UVM_FATAL @ 17743918190 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 17743918190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Test hmac_stress_all_with_rand_reset has 2 failures.

5.hmac_stress_all_with_rand_reset.50391629225992525282885721224728842356276366261967544928313214881775604770752
Line 6961, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 25327705849 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @ 25327705849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.hmac_stress_all_with_rand_reset.13821023789702943959107841487741178800817268046465054103691789550562330116797
Line 251, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   6921659 ps: (hmac_test_vectors_sha_vseq.sv:28) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] This test sequence requires a command-line argument: sha2_digest_size=SHA2_256/SHA2_384/SHA2_512
  UVM_INFO @   6921659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test hmac_stress_all_with_rand_reset has 6 failures.
  - 0.hmac_stress_all_with_rand_reset.17630344002228712477599178462719420205844950609947948239784876986651857427739
    Line 18744, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19583076060 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19583076060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.90780192160477619363888242265188439799803431799143854337567245705359961295965
    Line 22842, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19482453264 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19482453264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test hmac_test_sha512_vectors has 2 failures.
  - 6.hmac_test_sha512_vectors.43766628253015640154388394406072116688537671785873030409568374639405050055156
    Line 207384, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.hmac_test_sha512_vectors.40636626287030468279623590850773563205172498437009971079003580873964231917873
    Line 295439, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_test_sha384_vectors has 2 failures.
  - 24.hmac_test_sha384_vectors.39803644547326925772614604252423228369502049574340223895916763308991185672723
    Line 177048, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/24.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.hmac_test_sha384_vectors.96532141531824972360757184412161801310648600425182312182165931334022639577462
    Line 265193, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/34.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```