HMAC Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	12.400s	2.680ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.990s	43.985us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.990s	132.822us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	17.860s	3.281ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.920s	454.450us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.049m	646.846ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.990s	132.822us	20	20	100.00
		hmac_csr_aliasing	8.920s	454.450us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.781m	113.628ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.017m	2.435ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	9.704m	168.082ms	50	50	100.00
		hmac_test_hmac_vectors	1.590s	80.084us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.824m	112.727ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	21.534m	15.414ms	50	50	100.00
V2	error	hmac_error	3.607m	11.988ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.847m	22.536ms	50	50	100.00
V2	save_and_restore	save_and_restore			0	0	--
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	wide_digest_configurable_key_length			0	0	--
V2	stress_all	hmac_stress_all	1.701h	3.926s	50	50	100.00
V2	alert_test	hmac_alert_test	0.680s	16.189us	50	50	100.00
V2	intr_test	hmac_intr_test	0.670s	25.049us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.570s	321.389us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.570s	321.389us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.990s	43.985us	5	5	100.00
		hmac_csr_rw	0.990s	132.822us	20	20	100.00
		hmac_csr_aliasing	8.920s	454.450us	5	5	100.00
		hmac_same_csr_outstanding	2.390s	589.070us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.990s	43.985us	5	5	100.00
		hmac_csr_rw	0.990s	132.822us	20	20	100.00
		hmac_csr_aliasing	8.920s	454.450us	5	5	100.00
		hmac_same_csr_outstanding	2.390s	589.070us	20	20	100.00
V2		TOTAL			590	590	100.00
V2S	tl_intg_err	hmac_sec_cm	1.190s	997.366us	5	5	100.00
		hmac_tl_intg_err	4.630s	1.144ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.630s	1.144ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	12.400s	2.680ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.966h	481.878ms	8	200	4.00
V3		TOTAL			8	200	4.00
		TOTAL			728	920	79.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	13	13	81.25
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.26	94.84	92.14	100.00	76.92	89.38	99.49	72.04

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 191 failures:
  • Test hmac_stress_all_with_rand_reset has 191 failures.

    • 0.hmac_stress_all_with_rand_reset.47690357242311548559466126358310885500804606982591063550523249049902347884356
      Line 29428, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13119276942 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13119276942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.hmac_stress_all_with_rand_reset.67213511341494339846292802465132516664147158745268903553650099426078274788754
      Line 42747, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15327137250 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 15327137250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 189 more failures.

• UVM_ERROR (cip_base_vseq.sv:752) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 86.hmac_stress_all_with_rand_reset.109338207654050600157277919277147155308836130857757258004675523501574758094535
      Line 263, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/86.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  87214904 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @  87214904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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