HMAC Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.600s	2.801ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.010s	129.412us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.010s	31.036us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	17.920s	1.767ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.100s	153.977us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	18.403m	159.854ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.010s	31.036us	20	20	100.00
		hmac_csr_aliasing	8.100s	153.977us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.636m	95.375ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.278m	6.134ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	10.064m	87.962ms	50	50	100.00
		hmac_test_hmac_vectors	1.500s	79.354us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.262m	22.111ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	23.154m	4.661ms	50	50	100.00
V2	error	hmac_error	3.984m	49.076ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.876m	48.097ms	50	50	100.00
V2	save_and_restore	save_and_restore			0	0	--
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	wide_digest_configurable_key_length			0	0	--
V2	stress_all	hmac_stress_all	1.528h	244.584ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.650s	13.254us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	18.494us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.120s	146.280us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.120s	146.280us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.010s	129.412us	5	5	100.00
		hmac_csr_rw	1.010s	31.036us	20	20	100.00
		hmac_csr_aliasing	8.100s	153.977us	5	5	100.00
		hmac_same_csr_outstanding	2.540s	155.460us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.010s	129.412us	5	5	100.00
		hmac_csr_rw	1.010s	31.036us	20	20	100.00
		hmac_csr_aliasing	8.100s	153.977us	5	5	100.00
		hmac_same_csr_outstanding	2.540s	155.460us	20	20	100.00
V2		TOTAL			590	590	100.00
V2S	tl_intg_err	hmac_sec_cm	1.340s	584.694us	5	5	100.00
		hmac_tl_intg_err	4.580s	461.814us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.580s	461.814us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.600s	2.801ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.790h	436.972ms	3	200	1.50
V3		TOTAL			3	200	1.50
		TOTAL			723	920	78.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	13	13	81.25
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.50	94.84	92.25	100.00	71.79	89.38	99.49	71.75

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 197 failures:
  • Test hmac_stress_all_with_rand_reset has 197 failures.

    • 0.hmac_stress_all_with_rand_reset.34380970713665954615612130655687425975013940975353269698899727253765148693972
      Line 2148, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6810746205 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6810746205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.hmac_stress_all_with_rand_reset.72012269603937459692402633806775886602896256638419555482977253222825322068763
      Line 28785, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9343405578 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9343405578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 195 more failures.

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