HMAC Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 18.910s 3.988ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.010s 43.085us 5 5 100.00
V1 csr_rw hmac_csr_rw 1.030s 61.734us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 17.070s 1.643ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 8.340s 1.762ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 26.105m 619.406ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.030s 61.734us 20 20 100.00
hmac_csr_aliasing 8.340s 1.762ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 2.504m 11.265ms 50 50 100.00
V2 back_pressure hmac_back_pressure 59.960s 5.059ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 9.467m 83.274ms 50 50 100.00
hmac_test_sha384_vectors 38.212m 173.286ms 48 50 96.00
hmac_test_sha512_vectors 36.089m 705.273ms 47 50 94.00
hmac_test_hmac_vectors 1.500s 168.844us 50 50 100.00
V2 burst_wr hmac_burst_wr 1.198m 12.276ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 24.359m 5.096ms 50 50 100.00
V2 error hmac_error 3.284m 64.176ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 1.467m 2.098ms 50 50 100.00
V2 save_and_restore hmac_smoke 18.910s 3.988ms 50 50 100.00
hmac_long_msg 2.504m 11.265ms 50 50 100.00
hmac_back_pressure 59.960s 5.059ms 50 50 100.00
hmac_datapath_stress 24.359m 5.096ms 50 50 100.00
hmac_burst_wr 1.198m 12.276ms 50 50 100.00
hmac_stress_all 39.008m 29.524ms 8 50 16.00
V2 fifo_empty_status_interrupt fifo_empty_status_interrupt 0 0 --
V2 wide_digest_configurable_key_length hmac_smoke 18.910s 3.988ms 50 50 100.00
hmac_long_msg 2.504m 11.265ms 50 50 100.00
hmac_back_pressure 59.960s 5.059ms 50 50 100.00
hmac_datapath_stress 24.359m 5.096ms 50 50 100.00
hmac_burst_wr 1.198m 12.276ms 50 50 100.00
hmac_error 3.284m 64.176ms 50 50 100.00
hmac_wipe_secret 1.467m 2.098ms 50 50 100.00
hmac_test_sha256_vectors 9.467m 83.274ms 50 50 100.00
hmac_test_sha384_vectors 38.212m 173.286ms 48 50 96.00
hmac_test_sha512_vectors 36.089m 705.273ms 47 50 94.00
hmac_test_hmac_vectors 1.500s 168.844us 50 50 100.00
hmac_stress_all 39.008m 29.524ms 8 50 16.00
V2 stress_all hmac_stress_all 39.008m 29.524ms 8 50 16.00
V2 alert_test hmac_alert_test 0.690s 23.517us 50 50 100.00
V2 intr_test hmac_intr_test 0.720s 33.235us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.220s 226.300us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.220s 226.300us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.010s 43.085us 5 5 100.00
hmac_csr_rw 1.030s 61.734us 20 20 100.00
hmac_csr_aliasing 8.340s 1.762ms 5 5 100.00
hmac_same_csr_outstanding 2.370s 154.769us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.010s 43.085us 5 5 100.00
hmac_csr_rw 1.030s 61.734us 20 20 100.00
hmac_csr_aliasing 8.340s 1.762ms 5 5 100.00
hmac_same_csr_outstanding 2.370s 154.769us 20 20 100.00
V2 TOTAL 643 690 93.19
V2S tl_intg_err hmac_sec_cm 1.010s 424.708us 5 5 100.00
hmac_tl_intg_err 4.480s 253.493us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.480s 253.493us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 18.910s 3.988ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 20.064m 123.617ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 773 830 93.13

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 15 12 75.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.58 95.85 93.09 100.00 74.36 91.89 99.49 93.40

Failure Buckets

Past Results