HMAC Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	31.860s	10.203ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.000s	75.481us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	105.422us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	10.670s	910.184us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.640s	584.270us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	17.978m	442.871ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	105.422us	20	20	100.00
		hmac_csr_aliasing	8.640s	584.270us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.631m	63.285ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	53.070s	2.210ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.037m	46.644ms	50	50	100.00
		hmac_test_sha384_vectors	36.885m	702.794ms	47	50	94.00
		hmac_test_sha512_vectors	35.628m	184.272ms	47	50	94.00
		hmac_test_hmac_vectors	1.480s	85.437us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.291m	5.576ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	25.364m	10.217ms	50	50	100.00
V2	error	hmac_error	4.061m	40.622ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.740m	27.626ms	50	50	100.00
V2	save_and_restore	hmac_smoke	31.860s	10.203ms	50	50	100.00
		hmac_long_msg	2.631m	63.285ms	50	50	100.00
		hmac_back_pressure	53.070s	2.210ms	50	50	100.00
		hmac_datapath_stress	25.364m	10.217ms	50	50	100.00
		hmac_burst_wr	1.291m	5.576ms	50	50	100.00
		hmac_stress_all	2.111h	1.939s	50	50	100.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	31.860s	10.203ms	50	50	100.00
		hmac_long_msg	2.631m	63.285ms	50	50	100.00
		hmac_back_pressure	53.070s	2.210ms	50	50	100.00
		hmac_datapath_stress	25.364m	10.217ms	50	50	100.00
		hmac_burst_wr	1.291m	5.576ms	50	50	100.00
		hmac_error	4.061m	40.622ms	50	50	100.00
		hmac_wipe_secret	1.740m	27.626ms	50	50	100.00
		hmac_test_sha256_vectors	10.037m	46.644ms	50	50	100.00
		hmac_test_sha384_vectors	36.885m	702.794ms	47	50	94.00
		hmac_test_sha512_vectors	35.628m	184.272ms	47	50	94.00
		hmac_test_hmac_vectors	1.480s	85.437us	50	50	100.00
		hmac_stress_all	2.111h	1.939s	50	50	100.00
V2	stress_all	hmac_stress_all	2.111h	1.939s	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	15.723us	50	50	100.00
V2	intr_test	hmac_intr_test	0.670s	65.923us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.450s	79.764us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.450s	79.764us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.000s	75.481us	5	5	100.00
		hmac_csr_rw	0.970s	105.422us	20	20	100.00
		hmac_csr_aliasing	8.640s	584.270us	5	5	100.00
		hmac_same_csr_outstanding	2.530s	115.581us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.000s	75.481us	5	5	100.00
		hmac_csr_rw	0.970s	105.422us	20	20	100.00
		hmac_csr_aliasing	8.640s	584.270us	5	5	100.00
		hmac_same_csr_outstanding	2.530s	115.581us	20	20	100.00
V2		TOTAL			684	690	99.13
V2S	tl_intg_err	hmac_sec_cm	0.990s	92.114us	5	5	100.00
		hmac_tl_intg_err	4.510s	275.701us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.510s	275.701us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	31.860s	10.203ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	23.412m	26.415ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			815	830	98.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	15	13	81.25
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.06	95.94	94.34	100.00	82.05	92.33	99.49	94.27

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test hmac_stress_all_with_rand_reset has 9 failures.
  - 0.hmac_stress_all_with_rand_reset.3011702437832603062402539180888101851802103050901541864284301346103153545245
    Line 762, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 166193305 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 166193305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.64805893177935393069808163299899561253824212068250777829115021898077955891962
    Line 22895, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47699604713 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 47699604713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
- Test hmac_test_sha512_vectors has 3 failures.
  - 0.hmac_test_sha512_vectors.38119171552367182234018572650646919269086743554153146360643243634046291617769
    Line 277730, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.hmac_test_sha512_vectors.106919250666438090323212957726143282021991708123579168585704063421067892248409
    Line 200555, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test hmac_test_sha384_vectors has 3 failures.
  - 11.hmac_test_sha384_vectors.50785587075131350373323810483999651735913454845664728871347271919322419864107
    Line 214366, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.hmac_test_sha384_vectors.105349207977001608862942322254960933915810227129357747268220384405562204492417
    Line 113952, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/21.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

HMAC Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8db2a18db1`