HMAC Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	22.070s	4.975ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.960s	72.599us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.990s	35.137us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.780s	1.426ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.350s	1.590ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	2.910s	49.819us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.990s	35.137us	20	20	100.00
		hmac_csr_aliasing	6.350s	1.590ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.417m	54.030ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	55.930s	4.029ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	9.526m	43.267ms	50	50	100.00
		hmac_test_sha384_vectors	39.712m	422.882ms	49	50	98.00
		hmac_test_sha512_vectors	37.830m	736.406ms	49	50	98.00
		hmac_test_hmac_vectors			0	0	--
V2	burst_wr	hmac_burst_wr	1.335m	63.601ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	27.011m	10.091ms	50	50	100.00
V2	error	hmac_error	3.773m	13.050ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.785m	8.405ms	50	50	100.00
V2	save_and_restore	hmac_smoke	22.070s	4.975ms	50	50	100.00
		hmac_long_msg	2.417m	54.030ms	50	50	100.00
		hmac_back_pressure	55.930s	4.029ms	50	50	100.00
		hmac_datapath_stress	27.011m	10.091ms	50	50	100.00
		hmac_burst_wr	1.335m	63.601ms	50	50	100.00
		hmac_stress_all	2.956h	537.345ms	44	50	88.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	22.070s	4.975ms	50	50	100.00
		hmac_long_msg	2.417m	54.030ms	50	50	100.00
		hmac_back_pressure	55.930s	4.029ms	50	50	100.00
		hmac_datapath_stress	27.011m	10.091ms	50	50	100.00
		hmac_burst_wr	1.335m	63.601ms	50	50	100.00
		hmac_error	3.773m	13.050ms	50	50	100.00
		hmac_wipe_secret	1.785m	8.405ms	50	50	100.00
		hmac_test_sha256_vectors	9.526m	43.267ms	50	50	100.00
		hmac_test_sha384_vectors	39.712m	422.882ms	49	50	98.00
		hmac_test_sha512_vectors	37.830m	736.406ms	49	50	98.00
		hmac_stress_all	2.956h	537.345ms	44	50	88.00
		hmac_test_hmac_vectors			0	0	--
V2	stress_all	hmac_stress_all	2.956h	537.345ms	44	50	88.00
V2	alert_test	hmac_alert_test	0.630s	46.693us	50	50	100.00
V2	intr_test	hmac_intr_test	0.710s	17.645us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.620s	834.888us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.620s	834.888us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.960s	72.599us	5	5	100.00
		hmac_csr_rw	0.990s	35.137us	20	20	100.00
		hmac_csr_aliasing	6.350s	1.590ms	5	5	100.00
		hmac_same_csr_outstanding	2.590s	148.639us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.960s	72.599us	5	5	100.00
		hmac_csr_rw	0.990s	35.137us	20	20	100.00
		hmac_csr_aliasing	6.350s	1.590ms	5	5	100.00
		hmac_same_csr_outstanding	2.590s	148.639us	20	20	100.00
V2		TOTAL			632	640	98.75
V2S	tl_intg_err	hmac_sec_cm	0.990s	88.982us	5	5	100.00
		hmac_tl_intg_err	5.010s	671.542us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.010s	671.542us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	22.070s	4.975ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	29.096m	36.406ms	1	10	10.00
V3		TOTAL			1	10	10.00
	Unmapped tests	hmac_test_hmac256_vectors	1.269m	16.453ms	50	50	100.00
		hmac_test_hmac384_vectors	1.643m	19.527ms	50	50	100.00
		hmac_test_hmac512_vectors	2.128m	45.740ms	50	50	100.00
		TOTAL			913	930	98.17

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	3	3	3	100.00
V1	6	6	6	100.00
V2	16	14	11	68.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.67	95.94	94.34	100.00	79.49	92.33	99.49	94.10

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test hmac_stress_all_with_rand_reset has 9 failures.
  - 0.hmac_stress_all_with_rand_reset.34326034260363671117083385440240114868364334274546772653147021129300502357619
    Line 3030, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11969416310 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11969416310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.2808844713054771100795904510697195680035908578548960768568509663559189153994
    Line 56907, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33790905925 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33790905925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (hmac_scoreboard.sv:403) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 6 failures:

Test hmac_stress_all has 6 failures.

2.hmac_stress_all.103730410651380832104105413385520599958244798319802049251461061054886567974762
Line 361240, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log

  UVM_ERROR @ 335683846090 ps: (hmac_scoreboard.sv:403) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2400109349 [0x8f0ec325] vs 695868798 [0x297a1d7e])
  UVM_INFO @ 335683846090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.hmac_stress_all.36005876465947787974869149770295627477326715556010865719702628229476840485756
Line 84129, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_stress_all/latest/run.log

  UVM_ERROR @ 27698122460 ps: (hmac_scoreboard.sv:403) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1385860349 [0x529a8cfd] vs 3169382122 [0xbce8eeea])
  UVM_INFO @ 27698122460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test hmac_test_sha384_vectors has 1 failures.
  - 14.hmac_test_sha384_vectors.95302909055783423974294255956234393471511277955489887375021835866617418803852
    Line 281329, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_test_sha512_vectors has 1 failures.
  - 16.hmac_test_sha512_vectors.4098720540068193043883167159140174368190193586231398861403816400851530365431
    Line 270715, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```