HMAC Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.550s	3.126ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.000s	145.939us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.980s	33.883us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.520s	1.858ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.190s	3.305ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	10.948m	254.888ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.980s	33.883us	20	20	100.00
		hmac_csr_aliasing	6.190s	3.305ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.571m	38.419ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	55.100s	4.586ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	9.857m	85.347ms	50	50	100.00
		hmac_test_sha384_vectors	37.726m	172.205ms	49	50	98.00
		hmac_test_sha512_vectors	36.339m	309.434ms	46	50	92.00
		hmac_test_hmac_vectors			0	0	--
V2	burst_wr	hmac_burst_wr	1.241m	2.815ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	26.563m	37.653ms	50	50	100.00
V2	error	hmac_error	3.506m	3.675ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.773m	15.840ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.550s	3.126ms	50	50	100.00
		hmac_long_msg	2.571m	38.419ms	50	50	100.00
		hmac_back_pressure	55.100s	4.586ms	50	50	100.00
		hmac_datapath_stress	26.563m	37.653ms	50	50	100.00
		hmac_burst_wr	1.241m	2.815ms	50	50	100.00
		hmac_stress_all	1.814h	101.822ms	49	50	98.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	17.550s	3.126ms	50	50	100.00
		hmac_long_msg	2.571m	38.419ms	50	50	100.00
		hmac_back_pressure	55.100s	4.586ms	50	50	100.00
		hmac_datapath_stress	26.563m	37.653ms	50	50	100.00
		hmac_burst_wr	1.241m	2.815ms	50	50	100.00
		hmac_error	3.506m	3.675ms	50	50	100.00
		hmac_wipe_secret	1.773m	15.840ms	50	50	100.00
		hmac_test_sha256_vectors	9.857m	85.347ms	50	50	100.00
		hmac_test_sha384_vectors	37.726m	172.205ms	49	50	98.00
		hmac_test_sha512_vectors	36.339m	309.434ms	46	50	92.00
		hmac_stress_all	1.814h	101.822ms	49	50	98.00
		hmac_test_hmac_vectors			0	0	--
V2	stress_all	hmac_stress_all	1.814h	101.822ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.630s	18.000us	50	50	100.00
V2	intr_test	hmac_intr_test	0.700s	73.367us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.960s	78.206us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.960s	78.206us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.000s	145.939us	5	5	100.00
		hmac_csr_rw	0.980s	33.883us	20	20	100.00
		hmac_csr_aliasing	6.190s	3.305ms	5	5	100.00
		hmac_same_csr_outstanding	2.740s	125.417us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.000s	145.939us	5	5	100.00
		hmac_csr_rw	0.980s	33.883us	20	20	100.00
		hmac_csr_aliasing	6.190s	3.305ms	5	5	100.00
		hmac_same_csr_outstanding	2.740s	125.417us	20	20	100.00
V2		TOTAL			634	640	99.06
V2S	tl_intg_err	hmac_sec_cm	1.100s	168.703us	5	5	100.00
		hmac_tl_intg_err	4.350s	232.699us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.350s	232.699us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.550s	3.126ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	44.279m	215.239ms	0	10	0.00
V3		TOTAL			0	10	0.00
	Unmapped tests	hmac_test_hmac256_vectors	1.212m	37.384ms	50	50	100.00
		hmac_test_hmac384_vectors	1.631m	34.029ms	50	50	100.00
		hmac_test_hmac512_vectors	2.191m	61.823ms	50	50	100.00
		TOTAL			914	930	98.28

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	3	3	3	100.00
V1	6	6	6	100.00
V2	16	14	11	68.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.61	95.85	92.94	100.00	74.36	91.89	99.49	93.75

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test hmac_stress_all_with_rand_reset has 9 failures.
  - 0.hmac_stress_all_with_rand_reset.61898386954314125939281443016676414437512264812013762045562895255733398030410
    Line 936, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 244765503 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 244765503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.34428570676530044342147123835300755781794181651380463406876677466054055723404
    Line 32425, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2160212328 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2160212328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
- Test hmac_test_sha512_vectors has 4 failures.
  - 5.hmac_test_sha512_vectors.74546452685393604744990278420671123003122809057419309909540424164543017003687
    Line 116774, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.hmac_test_sha512_vectors.76076906017623063608533793241259473645497475027242473091029283973370618631277
    Line 193306, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/21.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test hmac_test_sha384_vectors has 1 failures.
  - 49.hmac_test_sha384_vectors.65429188516315039472140150223039537151612945623533193417097813203886813132212
    Line 189867, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/49.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_scoreboard.sv:403) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 2 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 6.hmac_stress_all_with_rand_reset.43643074307975270885881714578221356981119856175371625358656793542617947529697
    Line 25604, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2263394824 ps: (hmac_scoreboard.sv:403) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2457800741 [0x927f1025] vs 2808131640 [0xa760b038])
  UVM_INFO @ 2263394824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_stress_all has 1 failures.
  - 42.hmac_stress_all.37028137541549448968787361364022929774143259168201056090182138228125345454677
    Line 5111, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/42.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 4247536093 ps: (hmac_scoreboard.sv:403) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (233712368 [0xdee2af0] vs 639359941 [0x261bdbc5])
  UVM_INFO @ 4247536093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `b33f0bcb4a`