HMAC Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	18.700s	4.242ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.970s	37.635us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.000s	30.495us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.620s	322.882us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.310s	388.264us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	17.589m	227.958ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.000s	30.495us	20	20	100.00
		hmac_csr_aliasing	6.310s	388.264us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.111m	47.265ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.164m	24.976ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	9.498m	40.068ms	50	50	100.00
		hmac_test_sha384_vectors	36.890m	583.627ms	48	50	96.00
		hmac_test_sha512_vectors	39.178m	358.930ms	48	50	96.00
		hmac_test_hmac_vectors			0	0	--
V2	burst_wr	hmac_burst_wr	1.363m	4.515ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	26.137m	32.262ms	50	50	100.00
V2	error	hmac_error	2.744m	93.743ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.795m	15.506ms	50	50	100.00
V2	save_and_restore	hmac_smoke	18.700s	4.242ms	50	50	100.00
		hmac_long_msg	2.111m	47.265ms	50	50	100.00
		hmac_back_pressure	1.164m	24.976ms	50	50	100.00
		hmac_datapath_stress	26.137m	32.262ms	50	50	100.00
		hmac_burst_wr	1.363m	4.515ms	50	50	100.00
		hmac_stress_all	2.049h	1.813s	44	50	88.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	18.700s	4.242ms	50	50	100.00
		hmac_long_msg	2.111m	47.265ms	50	50	100.00
		hmac_back_pressure	1.164m	24.976ms	50	50	100.00
		hmac_datapath_stress	26.137m	32.262ms	50	50	100.00
		hmac_burst_wr	1.363m	4.515ms	50	50	100.00
		hmac_error	2.744m	93.743ms	50	50	100.00
		hmac_wipe_secret	1.795m	15.506ms	50	50	100.00
		hmac_test_sha256_vectors	9.498m	40.068ms	50	50	100.00
		hmac_test_sha384_vectors	36.890m	583.627ms	48	50	96.00
		hmac_test_sha512_vectors	39.178m	358.930ms	48	50	96.00
		hmac_stress_all	2.049h	1.813s	44	50	88.00
		hmac_test_hmac_vectors			0	0	--
V2	stress_all	hmac_stress_all	2.049h	1.813s	44	50	88.00
V2	alert_test	hmac_alert_test	0.660s	14.130us	50	50	100.00
V2	intr_test	hmac_intr_test	0.630s	46.158us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.410s	2.544ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.410s	2.544ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.970s	37.635us	5	5	100.00
		hmac_csr_rw	1.000s	30.495us	20	20	100.00
		hmac_csr_aliasing	6.310s	388.264us	5	5	100.00
		hmac_same_csr_outstanding	2.390s	553.852us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.970s	37.635us	5	5	100.00
		hmac_csr_rw	1.000s	30.495us	20	20	100.00
		hmac_csr_aliasing	6.310s	388.264us	5	5	100.00
		hmac_same_csr_outstanding	2.390s	553.852us	20	20	100.00
V2		TOTAL			630	640	98.44
V2S	tl_intg_err	hmac_sec_cm	1.020s	367.528us	5	5	100.00
		hmac_tl_intg_err	4.730s	1.129ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.730s	1.129ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	18.700s	4.242ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	22.643m	51.519ms	1	10	10.00
V3		TOTAL			1	10	10.00
	Unmapped tests	hmac_test_hmac256_vectors	1.254m	23.801ms	50	50	100.00
		hmac_test_hmac384_vectors	1.637m	17.185ms	50	50	100.00
		hmac_test_hmac512_vectors	2.159m	10.965ms	50	50	100.00
		TOTAL			911	930	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	3	3	3	100.00
V1	6	6	6	100.00
V2	16	14	11	68.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.23	95.94	94.18	100.00	76.92	92.33	99.49	93.75

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test hmac_stress_all_with_rand_reset has 9 failures.
  - 0.hmac_stress_all_with_rand_reset.97648402987865191176856491658528158945699078729757949422261317120642927732118
    Line 30647, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8976180372 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8976180372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.43626252542596037592270613623219154587783880754426306939068574055707599981963
    Line 60849, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26363222932 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26363222932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (hmac_scoreboard.sv:403) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 5 failures:

Test hmac_stress_all has 5 failures.

10.hmac_stress_all.64528140952849848790827334195368072853387543327576083017082862041482417443316
Line 100703, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all/latest/run.log

  UVM_ERROR @ 244342945199 ps: (hmac_scoreboard.sv:403) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2811752819 [0xa797f173] vs 344910483 [0x148eea93])
  UVM_INFO @ 244342945199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.hmac_stress_all.3415059382786280691814686283665852629105659319201104645949582890524964233096
Line 367597, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/28.hmac_stress_all/latest/run.log

  UVM_ERROR @ 39259539469 ps: (hmac_scoreboard.sv:403) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (256077703 [0xf436f87] vs 4196037198 [0xfa1a724e])
  UVM_INFO @ 39259539469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test hmac_test_sha384_vectors has 2 failures.
  - 0.hmac_test_sha384_vectors.81020437531184865639725089581064631125318703720503295978162363976673852419181
    Line 195499, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.hmac_test_sha384_vectors.19181243455733957854113661657439671869743773486471988868198331965188053431479
    Line 87557, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_test_sha512_vectors has 2 failures.
  - 24.hmac_test_sha512_vectors.11415879408174426741533043961201733114936118732426957274763341402072971762272
    Line 255832, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/24.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.hmac_test_sha512_vectors.20887293791998662879406137460291075205681255281607407812236190947634519346443
    Line 234653, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/47.hmac_test_sha512_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job hmac-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test hmac_stress_all has 1 failures.
  - 37.hmac_stress_all.81483570364319563937126532341651813018154294821187107844940455864398387689162
    Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/37.hmac_stress_all/latest/run.log
```
  Job ID: smart:d203c604-10bc-4964-919c-323f11504c68
```