HMAC Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.750s	1.575ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.000s	50.117us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	100.355us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.210s	8.464ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.040s	2.690ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	8.871m	276.334ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	100.355us	20	20	100.00
		hmac_csr_aliasing	6.040s	2.690ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.466m	14.278ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.776m	8.316ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.851m	49.512ms	5	5	100.00
		hmac_test_sha384_vectors	43.212m	843.280ms	5	5	100.00
		hmac_test_sha512_vectors	45.305m	583.001ms	4	5	80.00
		hmac_test_hmac256_vectors	1.355m	28.539ms	5	5	100.00
		hmac_test_hmac384_vectors	1.819m	18.008ms	5	5	100.00
		hmac_test_hmac512_vectors	2.354m	63.669ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.180m	2.606ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	28.306m	16.359ms	50	50	100.00
V2	error	hmac_error	3.885m	50.575ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.628m	12.437ms	50	50	100.00
V2	save_and_restore	hmac_smoke	15.750s	1.575ms	50	50	100.00
		hmac_long_msg	3.466m	14.278ms	50	50	100.00
		hmac_back_pressure	1.776m	8.316ms	50	50	100.00
		hmac_datapath_stress	28.306m	16.359ms	50	50	100.00
		hmac_burst_wr	1.180m	2.606ms	50	50	100.00
		hmac_stress_all	1.168h	127.457ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.750s	1.575ms	50	50	100.00
		hmac_long_msg	3.466m	14.278ms	50	50	100.00
		hmac_back_pressure	1.776m	8.316ms	50	50	100.00
		hmac_datapath_stress	28.306m	16.359ms	50	50	100.00
		hmac_wipe_secret	2.628m	12.437ms	50	50	100.00
		hmac_test_sha256_vectors	11.851m	49.512ms	5	5	100.00
		hmac_test_sha384_vectors	43.212m	843.280ms	5	5	100.00
		hmac_test_sha512_vectors	45.305m	583.001ms	4	5	80.00
		hmac_test_hmac256_vectors	1.355m	28.539ms	5	5	100.00
		hmac_test_hmac384_vectors	1.819m	18.008ms	5	5	100.00
		hmac_test_hmac512_vectors	2.354m	63.669ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.750s	1.575ms	50	50	100.00
		hmac_long_msg	3.466m	14.278ms	50	50	100.00
		hmac_back_pressure	1.776m	8.316ms	50	50	100.00
		hmac_datapath_stress	28.306m	16.359ms	50	50	100.00
		hmac_burst_wr	1.180m	2.606ms	50	50	100.00
		hmac_error	3.885m	50.575ms	50	50	100.00
		hmac_wipe_secret	2.628m	12.437ms	50	50	100.00
		hmac_test_sha256_vectors	11.851m	49.512ms	5	5	100.00
		hmac_test_sha384_vectors	43.212m	843.280ms	5	5	100.00
		hmac_test_sha512_vectors	45.305m	583.001ms	4	5	80.00
		hmac_test_hmac256_vectors	1.355m	28.539ms	5	5	100.00
		hmac_test_hmac384_vectors	1.819m	18.008ms	5	5	100.00
		hmac_test_hmac512_vectors	2.354m	63.669ms	5	5	100.00
		hmac_stress_all	1.168h	127.457ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.168h	127.457ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.760s	24.040us	50	50	100.00
V2	intr_test	hmac_intr_test	0.690s	54.629us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.880s	402.037us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.880s	402.037us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.000s	50.117us	5	5	100.00
		hmac_csr_rw	0.970s	100.355us	20	20	100.00
		hmac_csr_aliasing	6.040s	2.690ms	5	5	100.00
		hmac_same_csr_outstanding	2.470s	1.254ms	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.000s	50.117us	5	5	100.00
		hmac_csr_rw	0.970s	100.355us	20	20	100.00
		hmac_csr_aliasing	6.040s	2.690ms	5	5	100.00
		hmac_same_csr_outstanding	2.470s	1.254ms	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.110s	115.492us	5	5	100.00
		hmac_tl_intg_err	4.680s	284.827us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.680s	284.827us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.750s	1.575ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.707h	893.656ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			659	660	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	95.40	97.22	100.00	94.12	98.27	98.48	99.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test hmac_test_sha512_vectors has 1 failures.

    • 2.hmac_test_sha512_vectors.115606519979499238420380469277485969938615824768372261052926086739033906618510
      Line 286223, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest/run.log

        UVM_FATAL @ 3500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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