HMAC Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.100s	1.192ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.000s	40.765us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.000s	132.716us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	17.370s	1.639ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.180s	2.479ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.948m	291.217ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.000s	132.716us	20	20	100.00
		hmac_csr_aliasing	8.180s	2.479ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.555m	47.961ms	49	50	98.00
V2	back_pressure	hmac_back_pressure	1.741m	1.704ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.267m	57.583ms	5	5	100.00
		hmac_test_sha384_vectors	42.354m	427.002ms	5	5	100.00
		hmac_test_sha512_vectors	41.946m	147.330ms	5	5	100.00
		hmac_test_hmac256_vectors	1.175m	17.239ms	5	5	100.00
		hmac_test_hmac384_vectors	1.679m	23.920ms	5	5	100.00
		hmac_test_hmac512_vectors	1.907m	11.912ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.273m	23.532ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	23.274m	7.246ms	50	50	100.00
V2	error	hmac_error	3.793m	17.836ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.318m	31.470ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.100s	1.192ms	50	50	100.00
		hmac_long_msg	3.555m	47.961ms	49	50	98.00
		hmac_back_pressure	1.741m	1.704ms	50	50	100.00
		hmac_datapath_stress	23.274m	7.246ms	50	50	100.00
		hmac_burst_wr	1.273m	23.532ms	49	50	98.00
		hmac_stress_all	1.517h	29.060ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.100s	1.192ms	50	50	100.00
		hmac_long_msg	3.555m	47.961ms	49	50	98.00
		hmac_back_pressure	1.741m	1.704ms	50	50	100.00
		hmac_datapath_stress	23.274m	7.246ms	50	50	100.00
		hmac_wipe_secret	2.318m	31.470ms	50	50	100.00
		hmac_test_sha256_vectors	11.267m	57.583ms	5	5	100.00
		hmac_test_sha384_vectors	42.354m	427.002ms	5	5	100.00
		hmac_test_sha512_vectors	41.946m	147.330ms	5	5	100.00
		hmac_test_hmac256_vectors	1.175m	17.239ms	5	5	100.00
		hmac_test_hmac384_vectors	1.679m	23.920ms	5	5	100.00
		hmac_test_hmac512_vectors	1.907m	11.912ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.100s	1.192ms	50	50	100.00
		hmac_long_msg	3.555m	47.961ms	49	50	98.00
		hmac_back_pressure	1.741m	1.704ms	50	50	100.00
		hmac_datapath_stress	23.274m	7.246ms	50	50	100.00
		hmac_burst_wr	1.273m	23.532ms	49	50	98.00
		hmac_error	3.793m	17.836ms	50	50	100.00
		hmac_wipe_secret	2.318m	31.470ms	50	50	100.00
		hmac_test_sha256_vectors	11.267m	57.583ms	5	5	100.00
		hmac_test_sha384_vectors	42.354m	427.002ms	5	5	100.00
		hmac_test_sha512_vectors	41.946m	147.330ms	5	5	100.00
		hmac_test_hmac256_vectors	1.175m	17.239ms	5	5	100.00
		hmac_test_hmac384_vectors	1.679m	23.920ms	5	5	100.00
		hmac_test_hmac512_vectors	1.907m	11.912ms	5	5	100.00
		hmac_stress_all	1.517h	29.060ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.517h	29.060ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.650s	95.439us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	13.084us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.870s	2.316ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.870s	2.316ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.000s	40.765us	5	5	100.00
		hmac_csr_rw	1.000s	132.716us	20	20	100.00
		hmac_csr_aliasing	8.180s	2.479ms	5	5	100.00
		hmac_same_csr_outstanding	2.410s	284.049us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.000s	40.765us	5	5	100.00
		hmac_csr_rw	1.000s	132.716us	20	20	100.00
		hmac_csr_aliasing	8.180s	2.479ms	5	5	100.00
		hmac_same_csr_outstanding	2.410s	284.049us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	1.020s	86.386us	5	5	100.00
		hmac_tl_intg_err	4.480s	273.041us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.480s	273.041us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.100s	1.192ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.270h	82.287ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	95.40	97.22	100.00	94.12	98.27	98.48	99.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test hmac_long_msg has 1 failures.

    • 1.hmac_long_msg.53244288386703883783887210951047898198272083684621467187985509773992138420525
      Line 28427, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_long_msg/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:

  • Test hmac_burst_wr has 1 failures.

    • 6.hmac_burst_wr.93537060804469390452787496641800742999998762750313631833578121119500154072684
      Line 385, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 349012771 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 349012771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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