HMAC Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 17.010s 6.408ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.010s 198.713us 5 5 100.00
V1 csr_rw hmac_csr_rw 1.010s 51.035us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 17.280s 3.265ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 9.040s 931.020us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 23.113m 142.326ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.010s 51.035us 20 20 100.00
hmac_csr_aliasing 9.040s 931.020us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.976m 72.273ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.929m 7.893ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 11.761m 372.917ms 5 5 100.00
hmac_test_sha384_vectors 45.248m 229.003ms 5 5 100.00
hmac_test_sha512_vectors 45.077m 153.908ms 5 5 100.00
hmac_test_hmac256_vectors 1.356m 6.537ms 5 5 100.00
hmac_test_hmac384_vectors 1.662m 4.704ms 5 5 100.00
hmac_test_hmac512_vectors 2.082m 28.299ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.132m 10.372ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 25.136m 6.010ms 50 50 100.00
V2 error hmac_error 4.117m 13.655ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.374m 10.959ms 50 50 100.00
V2 save_and_restore hmac_smoke 17.010s 6.408ms 50 50 100.00
hmac_long_msg 3.976m 72.273ms 50 50 100.00
hmac_back_pressure 1.929m 7.893ms 50 50 100.00
hmac_datapath_stress 25.136m 6.010ms 50 50 100.00
hmac_burst_wr 1.132m 10.372ms 50 50 100.00
hmac_stress_all 1.613h 100.839ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 17.010s 6.408ms 50 50 100.00
hmac_long_msg 3.976m 72.273ms 50 50 100.00
hmac_back_pressure 1.929m 7.893ms 50 50 100.00
hmac_datapath_stress 25.136m 6.010ms 50 50 100.00
hmac_wipe_secret 2.374m 10.959ms 50 50 100.00
hmac_test_sha256_vectors 11.761m 372.917ms 5 5 100.00
hmac_test_sha384_vectors 45.248m 229.003ms 5 5 100.00
hmac_test_sha512_vectors 45.077m 153.908ms 5 5 100.00
hmac_test_hmac256_vectors 1.356m 6.537ms 5 5 100.00
hmac_test_hmac384_vectors 1.662m 4.704ms 5 5 100.00
hmac_test_hmac512_vectors 2.082m 28.299ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 17.010s 6.408ms 50 50 100.00
hmac_long_msg 3.976m 72.273ms 50 50 100.00
hmac_back_pressure 1.929m 7.893ms 50 50 100.00
hmac_datapath_stress 25.136m 6.010ms 50 50 100.00
hmac_burst_wr 1.132m 10.372ms 50 50 100.00
hmac_error 4.117m 13.655ms 50 50 100.00
hmac_wipe_secret 2.374m 10.959ms 50 50 100.00
hmac_test_sha256_vectors 11.761m 372.917ms 5 5 100.00
hmac_test_sha384_vectors 45.248m 229.003ms 5 5 100.00
hmac_test_sha512_vectors 45.077m 153.908ms 5 5 100.00
hmac_test_hmac256_vectors 1.356m 6.537ms 5 5 100.00
hmac_test_hmac384_vectors 1.662m 4.704ms 5 5 100.00
hmac_test_hmac512_vectors 2.082m 28.299ms 5 5 100.00
hmac_stress_all 1.613h 100.839ms 50 50 100.00
V2 stress_all hmac_stress_all 1.613h 100.839ms 50 50 100.00
V2 alert_test hmac_alert_test 0.640s 30.162us 50 50 100.00
V2 intr_test hmac_intr_test 0.690s 43.786us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.090s 195.962us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.090s 195.962us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.010s 198.713us 5 5 100.00
hmac_csr_rw 1.010s 51.035us 20 20 100.00
hmac_csr_aliasing 9.040s 931.020us 5 5 100.00
hmac_same_csr_outstanding 2.350s 111.548us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.010s 198.713us 5 5 100.00
hmac_csr_rw 1.010s 51.035us 20 20 100.00
hmac_csr_aliasing 9.040s 931.020us 5 5 100.00
hmac_same_csr_outstanding 2.350s 111.548us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.020s 955.192us 5 5 100.00
hmac_tl_intg_err 4.610s 267.977us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.610s 267.977us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 17.010s 6.408ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.035h 308.302ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.06 95.40 97.33 100.00 97.06 98.27 98.48 99.85

Past Results