HMAC Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.710s	678.420us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.880s	247.724us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.030s	29.214us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.480s	1.542ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.550s	1.028ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	3.145m	40.366ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.030s	29.214us	20	20	100.00
		hmac_csr_aliasing	8.550s	1.028ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.911m	51.382ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.823m	3.806ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.804m	233.007ms	4	5	80.00
		hmac_test_sha384_vectors	42.782m	758.986ms	5	5	100.00
		hmac_test_sha512_vectors	45.882m	215.139ms	5	5	100.00
		hmac_test_hmac256_vectors	1.173m	17.022ms	5	5	100.00
		hmac_test_hmac384_vectors	1.837m	6.740ms	5	5	100.00
		hmac_test_hmac512_vectors	2.321m	34.294ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.209m	10.681ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	21.078m	84.477ms	50	50	100.00
V2	error	hmac_error	4.368m	22.573ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.729m	26.085ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.710s	678.420us	50	50	100.00
		hmac_long_msg	3.911m	51.382ms	50	50	100.00
		hmac_back_pressure	1.823m	3.806ms	50	50	100.00
		hmac_datapath_stress	21.078m	84.477ms	50	50	100.00
		hmac_burst_wr	1.209m	10.681ms	50	50	100.00
		hmac_stress_all	1.276h	374.625ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.710s	678.420us	50	50	100.00
		hmac_long_msg	3.911m	51.382ms	50	50	100.00
		hmac_back_pressure	1.823m	3.806ms	50	50	100.00
		hmac_datapath_stress	21.078m	84.477ms	50	50	100.00
		hmac_wipe_secret	2.729m	26.085ms	50	50	100.00
		hmac_test_sha256_vectors	11.804m	233.007ms	4	5	80.00
		hmac_test_sha384_vectors	42.782m	758.986ms	5	5	100.00
		hmac_test_sha512_vectors	45.882m	215.139ms	5	5	100.00
		hmac_test_hmac256_vectors	1.173m	17.022ms	5	5	100.00
		hmac_test_hmac384_vectors	1.837m	6.740ms	5	5	100.00
		hmac_test_hmac512_vectors	2.321m	34.294ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.710s	678.420us	50	50	100.00
		hmac_long_msg	3.911m	51.382ms	50	50	100.00
		hmac_back_pressure	1.823m	3.806ms	50	50	100.00
		hmac_datapath_stress	21.078m	84.477ms	50	50	100.00
		hmac_burst_wr	1.209m	10.681ms	50	50	100.00
		hmac_error	4.368m	22.573ms	50	50	100.00
		hmac_wipe_secret	2.729m	26.085ms	50	50	100.00
		hmac_test_sha256_vectors	11.804m	233.007ms	4	5	80.00
		hmac_test_sha384_vectors	42.782m	758.986ms	5	5	100.00
		hmac_test_sha512_vectors	45.882m	215.139ms	5	5	100.00
		hmac_test_hmac256_vectors	1.173m	17.022ms	5	5	100.00
		hmac_test_hmac384_vectors	1.837m	6.740ms	5	5	100.00
		hmac_test_hmac512_vectors	2.321m	34.294ms	5	5	100.00
		hmac_stress_all	1.276h	374.625ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.276h	374.625ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.630s	15.767us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	16.680us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.120s	229.368us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.120s	229.368us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.880s	247.724us	5	5	100.00
		hmac_csr_rw	1.030s	29.214us	20	20	100.00
		hmac_csr_aliasing	8.550s	1.028ms	5	5	100.00
		hmac_same_csr_outstanding	2.480s	150.748us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.880s	247.724us	5	5	100.00
		hmac_csr_rw	1.030s	29.214us	20	20	100.00
		hmac_csr_aliasing	8.550s	1.028ms	5	5	100.00
		hmac_same_csr_outstanding	2.480s	150.748us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	0.970s	145.771us	5	5	100.00
		hmac_tl_intg_err	4.560s	1.203ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.560s	1.203ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.710s	678.420us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.690h	62.873ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			657	660	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.04	95.40	97.22	100.00	97.06	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 8.hmac_stress_all_with_rand_reset.53856595505769973385295841784008339367619857814413142447104996568833621213446
    Line 537773, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 62873404268 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 62873404268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.hmac_stress_all_with_rand_reset.85234244115695085901508201225585361781180050943122365330419866450054391201652
    Line 77554, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9368889466 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 9368889466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test hmac_test_sha256_vectors has 1 failures.
  - 0.hmac_test_sha256_vectors.79687980748153731433585146824784332835330661133233731827909990493335570045365
    Line 73134, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest/run.log
```
  UVM_FATAL @ 800000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 800000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 800000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3e0219a2c5`