HMAC Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	14.900s	8.883ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.870s	26.733us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	29.723us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.270s	1.396ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.670s	509.735us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	23.959m	157.128ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	29.723us	20	20	100.00
		hmac_csr_aliasing	8.670s	509.735us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.475m	15.153ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.777m	7.663ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.923m	215.055ms	5	5	100.00
		hmac_test_sha384_vectors	40.283m	739.375ms	4	5	80.00
		hmac_test_sha512_vectors	43.464m	440.892ms	5	5	100.00
		hmac_test_hmac256_vectors	1.253m	17.243ms	5	5	100.00
		hmac_test_hmac384_vectors	1.799m	6.524ms	5	5	100.00
		hmac_test_hmac512_vectors	2.045m	6.358ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.333m	7.755ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	27.842m	34.047ms	50	50	100.00
V2	error	hmac_error	3.915m	3.932ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.280m	11.433ms	50	50	100.00
V2	save_and_restore	hmac_smoke	14.900s	8.883ms	50	50	100.00
		hmac_long_msg	3.475m	15.153ms	50	50	100.00
		hmac_back_pressure	1.777m	7.663ms	50	50	100.00
		hmac_datapath_stress	27.842m	34.047ms	50	50	100.00
		hmac_burst_wr	1.333m	7.755ms	49	50	98.00
		hmac_stress_all	55.789m	138.022ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	14.900s	8.883ms	50	50	100.00
		hmac_long_msg	3.475m	15.153ms	50	50	100.00
		hmac_back_pressure	1.777m	7.663ms	50	50	100.00
		hmac_datapath_stress	27.842m	34.047ms	50	50	100.00
		hmac_wipe_secret	2.280m	11.433ms	50	50	100.00
		hmac_test_sha256_vectors	11.923m	215.055ms	5	5	100.00
		hmac_test_sha384_vectors	40.283m	739.375ms	4	5	80.00
		hmac_test_sha512_vectors	43.464m	440.892ms	5	5	100.00
		hmac_test_hmac256_vectors	1.253m	17.243ms	5	5	100.00
		hmac_test_hmac384_vectors	1.799m	6.524ms	5	5	100.00
		hmac_test_hmac512_vectors	2.045m	6.358ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	14.900s	8.883ms	50	50	100.00
		hmac_long_msg	3.475m	15.153ms	50	50	100.00
		hmac_back_pressure	1.777m	7.663ms	50	50	100.00
		hmac_datapath_stress	27.842m	34.047ms	50	50	100.00
		hmac_burst_wr	1.333m	7.755ms	49	50	98.00
		hmac_error	3.915m	3.932ms	50	50	100.00
		hmac_wipe_secret	2.280m	11.433ms	50	50	100.00
		hmac_test_sha256_vectors	11.923m	215.055ms	5	5	100.00
		hmac_test_sha384_vectors	40.283m	739.375ms	4	5	80.00
		hmac_test_sha512_vectors	43.464m	440.892ms	5	5	100.00
		hmac_test_hmac256_vectors	1.253m	17.243ms	5	5	100.00
		hmac_test_hmac384_vectors	1.799m	6.524ms	5	5	100.00
		hmac_test_hmac512_vectors	2.045m	6.358ms	5	5	100.00
		hmac_stress_all	55.789m	138.022ms	50	50	100.00
V2	stress_all	hmac_stress_all	55.789m	138.022ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.670s	46.463us	50	50	100.00
V2	intr_test	hmac_intr_test	0.760s	12.478us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.980s	227.675us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.980s	227.675us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.870s	26.733us	5	5	100.00
		hmac_csr_rw	0.970s	29.723us	20	20	100.00
		hmac_csr_aliasing	8.670s	509.735us	5	5	100.00
		hmac_same_csr_outstanding	2.630s	152.750us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.870s	26.733us	5	5	100.00
		hmac_csr_rw	0.970s	29.723us	20	20	100.00
		hmac_csr_aliasing	8.670s	509.735us	5	5	100.00
		hmac_same_csr_outstanding	2.630s	152.750us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	0.930s	219.513us	5	5	100.00
		hmac_tl_intg_err	4.580s	448.297us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.580s	448.297us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	14.900s	8.883ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.842h	1.083s	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test hmac_test_sha384_vectors has 1 failures.
  - 0.hmac_test_sha384_vectors.106620493727265000898712593641960180664532166320100924976879985819971741923859
    Line 267591, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:
- Test hmac_burst_wr has 1 failures.
  - 46.hmac_burst_wr.15945497422638968474880070643612649355089463799124701343959543154109754872600
    Line 858, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/46.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 2895949906 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 2895949906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`