HMAC Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.780s	1.776ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.000s	45.204us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.950s	30.763us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.650s	2.097ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.570s	623.152us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	10.269m	65.344ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.950s	30.763us	20	20	100.00
		hmac_csr_aliasing	9.570s	623.152us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.522m	107.285ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.015m	21.598ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.616m	52.887ms	5	5	100.00
		hmac_test_sha384_vectors	40.287m	190.594ms	5	5	100.00
		hmac_test_sha512_vectors	41.457m	208.155ms	5	5	100.00
		hmac_test_hmac256_vectors	1.352m	18.770ms	5	5	100.00
		hmac_test_hmac384_vectors	1.683m	18.117ms	5	5	100.00
		hmac_test_hmac512_vectors	2.072m	6.367ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.300m	17.832ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	25.821m	35.886ms	50	50	100.00
V2	error	hmac_error	4.968m	21.537ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.658m	12.481ms	50	50	100.00
V2	save_and_restore	hmac_smoke	15.780s	1.776ms	50	50	100.00
		hmac_long_msg	3.522m	107.285ms	50	50	100.00
		hmac_back_pressure	2.015m	21.598ms	50	50	100.00
		hmac_datapath_stress	25.821m	35.886ms	50	50	100.00
		hmac_burst_wr	1.300m	17.832ms	50	50	100.00
		hmac_stress_all	1.419h	80.247ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.780s	1.776ms	50	50	100.00
		hmac_long_msg	3.522m	107.285ms	50	50	100.00
		hmac_back_pressure	2.015m	21.598ms	50	50	100.00
		hmac_datapath_stress	25.821m	35.886ms	50	50	100.00
		hmac_wipe_secret	2.658m	12.481ms	50	50	100.00
		hmac_test_sha256_vectors	11.616m	52.887ms	5	5	100.00
		hmac_test_sha384_vectors	40.287m	190.594ms	5	5	100.00
		hmac_test_sha512_vectors	41.457m	208.155ms	5	5	100.00
		hmac_test_hmac256_vectors	1.352m	18.770ms	5	5	100.00
		hmac_test_hmac384_vectors	1.683m	18.117ms	5	5	100.00
		hmac_test_hmac512_vectors	2.072m	6.367ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.780s	1.776ms	50	50	100.00
		hmac_long_msg	3.522m	107.285ms	50	50	100.00
		hmac_back_pressure	2.015m	21.598ms	50	50	100.00
		hmac_datapath_stress	25.821m	35.886ms	50	50	100.00
		hmac_burst_wr	1.300m	17.832ms	50	50	100.00
		hmac_error	4.968m	21.537ms	50	50	100.00
		hmac_wipe_secret	2.658m	12.481ms	50	50	100.00
		hmac_test_sha256_vectors	11.616m	52.887ms	5	5	100.00
		hmac_test_sha384_vectors	40.287m	190.594ms	5	5	100.00
		hmac_test_sha512_vectors	41.457m	208.155ms	5	5	100.00
		hmac_test_hmac256_vectors	1.352m	18.770ms	5	5	100.00
		hmac_test_hmac384_vectors	1.683m	18.117ms	5	5	100.00
		hmac_test_hmac512_vectors	2.072m	6.367ms	5	5	100.00
		hmac_stress_all	1.419h	80.247ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.419h	80.247ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.650s	174.225us	50	50	100.00
V2	intr_test	hmac_intr_test	0.650s	59.216us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.370s	400.141us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.370s	400.141us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.000s	45.204us	5	5	100.00
		hmac_csr_rw	0.950s	30.763us	20	20	100.00
		hmac_csr_aliasing	9.570s	623.152us	5	5	100.00
		hmac_same_csr_outstanding	2.670s	158.282us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.000s	45.204us	5	5	100.00
		hmac_csr_rw	0.950s	30.763us	20	20	100.00
		hmac_csr_aliasing	9.570s	623.152us	5	5	100.00
		hmac_same_csr_outstanding	2.670s	158.282us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	0.950s	115.264us	5	5	100.00
		hmac_tl_intg_err	4.640s	286.328us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.640s	286.328us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.780s	1.776ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.653h	122.535ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			659	660	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:
  • Test hmac_stress_all has 1 failures.

    • 0.hmac_stress_all.32091093419539373174553960708968057611159013847665277056946886140601971708730
      Line 5481, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log

        UVM_ERROR @ 2249299106 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 2249299106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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