HMAC Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 17.810s 1.393ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.990s 69.353us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.980s 27.875us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 16.160s 1.094ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 7.960s 665.300us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 23.711m 275.498ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.980s 27.875us 20 20 100.00
hmac_csr_aliasing 7.960s 665.300us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 4.083m 16.660ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.755m 7.593ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 11.157m 55.085ms 5 5 100.00
hmac_test_sha384_vectors 43.083m 816.333ms 5 5 100.00
hmac_test_sha512_vectors 41.971m 188.440ms 5 5 100.00
hmac_test_hmac256_vectors 1.186m 5.693ms 5 5 100.00
hmac_test_hmac384_vectors 1.899m 9.845ms 5 5 100.00
hmac_test_hmac512_vectors 2.335m 35.792ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.515m 13.532ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 22.998m 31.713ms 50 50 100.00
V2 error hmac_error 4.756m 10.260ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.811m 21.526ms 50 50 100.00
V2 save_and_restore hmac_smoke 17.810s 1.393ms 50 50 100.00
hmac_long_msg 4.083m 16.660ms 50 50 100.00
hmac_back_pressure 1.755m 7.593ms 50 50 100.00
hmac_datapath_stress 22.998m 31.713ms 50 50 100.00
hmac_burst_wr 1.515m 13.532ms 50 50 100.00
hmac_stress_all 1.659h 263.149ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 17.810s 1.393ms 50 50 100.00
hmac_long_msg 4.083m 16.660ms 50 50 100.00
hmac_back_pressure 1.755m 7.593ms 50 50 100.00
hmac_datapath_stress 22.998m 31.713ms 50 50 100.00
hmac_wipe_secret 2.811m 21.526ms 50 50 100.00
hmac_test_sha256_vectors 11.157m 55.085ms 5 5 100.00
hmac_test_sha384_vectors 43.083m 816.333ms 5 5 100.00
hmac_test_sha512_vectors 41.971m 188.440ms 5 5 100.00
hmac_test_hmac256_vectors 1.186m 5.693ms 5 5 100.00
hmac_test_hmac384_vectors 1.899m 9.845ms 5 5 100.00
hmac_test_hmac512_vectors 2.335m 35.792ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 17.810s 1.393ms 50 50 100.00
hmac_long_msg 4.083m 16.660ms 50 50 100.00
hmac_back_pressure 1.755m 7.593ms 50 50 100.00
hmac_datapath_stress 22.998m 31.713ms 50 50 100.00
hmac_burst_wr 1.515m 13.532ms 50 50 100.00
hmac_error 4.756m 10.260ms 50 50 100.00
hmac_wipe_secret 2.811m 21.526ms 50 50 100.00
hmac_test_sha256_vectors 11.157m 55.085ms 5 5 100.00
hmac_test_sha384_vectors 43.083m 816.333ms 5 5 100.00
hmac_test_sha512_vectors 41.971m 188.440ms 5 5 100.00
hmac_test_hmac256_vectors 1.186m 5.693ms 5 5 100.00
hmac_test_hmac384_vectors 1.899m 9.845ms 5 5 100.00
hmac_test_hmac512_vectors 2.335m 35.792ms 5 5 100.00
hmac_stress_all 1.659h 263.149ms 50 50 100.00
V2 stress_all hmac_stress_all 1.659h 263.149ms 50 50 100.00
V2 alert_test hmac_alert_test 0.630s 23.958us 50 50 100.00
V2 intr_test hmac_intr_test 0.630s 14.480us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.160s 162.701us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.160s 162.701us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.990s 69.353us 5 5 100.00
hmac_csr_rw 0.980s 27.875us 20 20 100.00
hmac_csr_aliasing 7.960s 665.300us 5 5 100.00
hmac_same_csr_outstanding 2.360s 170.535us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.990s 69.353us 5 5 100.00
hmac_csr_rw 0.980s 27.875us 20 20 100.00
hmac_csr_aliasing 7.960s 665.300us 5 5 100.00
hmac_same_csr_outstanding 2.360s 170.535us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.050s 140.101us 5 5 100.00
hmac_tl_intg_err 4.680s 284.491us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.680s 284.491us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 17.810s 1.393ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.616h 315.894ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85

Past Results