HMAC Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 16.850s 1.355ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.000s 138.143us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.970s 244.123us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 16.480s 1.643ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 8.880s 9.591ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 15.375m 264.738ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.970s 244.123us 20 20 100.00
hmac_csr_aliasing 8.880s 9.591ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.196m 28.864ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.729m 3.358ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 12.374m 245.283ms 5 5 100.00
hmac_test_sha384_vectors 43.042m 212.919ms 5 5 100.00
hmac_test_sha512_vectors 40.550m 889.418ms 5 5 100.00
hmac_test_hmac256_vectors 1.210m 6.202ms 5 5 100.00
hmac_test_hmac384_vectors 1.770m 6.646ms 5 5 100.00
hmac_test_hmac512_vectors 1.885m 18.985ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.195m 19.727ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 28.022m 8.906ms 50 50 100.00
V2 error hmac_error 4.475m 4.697ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.729m 28.950ms 50 50 100.00
V2 save_and_restore hmac_smoke 16.850s 1.355ms 50 50 100.00
hmac_long_msg 3.196m 28.864ms 50 50 100.00
hmac_back_pressure 1.729m 3.358ms 50 50 100.00
hmac_datapath_stress 28.022m 8.906ms 50 50 100.00
hmac_burst_wr 1.195m 19.727ms 50 50 100.00
hmac_stress_all 1.618h 69.347ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 16.850s 1.355ms 50 50 100.00
hmac_long_msg 3.196m 28.864ms 50 50 100.00
hmac_back_pressure 1.729m 3.358ms 50 50 100.00
hmac_datapath_stress 28.022m 8.906ms 50 50 100.00
hmac_wipe_secret 2.729m 28.950ms 50 50 100.00
hmac_test_sha256_vectors 12.374m 245.283ms 5 5 100.00
hmac_test_sha384_vectors 43.042m 212.919ms 5 5 100.00
hmac_test_sha512_vectors 40.550m 889.418ms 5 5 100.00
hmac_test_hmac256_vectors 1.210m 6.202ms 5 5 100.00
hmac_test_hmac384_vectors 1.770m 6.646ms 5 5 100.00
hmac_test_hmac512_vectors 1.885m 18.985ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 16.850s 1.355ms 50 50 100.00
hmac_long_msg 3.196m 28.864ms 50 50 100.00
hmac_back_pressure 1.729m 3.358ms 50 50 100.00
hmac_datapath_stress 28.022m 8.906ms 50 50 100.00
hmac_burst_wr 1.195m 19.727ms 50 50 100.00
hmac_error 4.475m 4.697ms 50 50 100.00
hmac_wipe_secret 2.729m 28.950ms 50 50 100.00
hmac_test_sha256_vectors 12.374m 245.283ms 5 5 100.00
hmac_test_sha384_vectors 43.042m 212.919ms 5 5 100.00
hmac_test_sha512_vectors 40.550m 889.418ms 5 5 100.00
hmac_test_hmac256_vectors 1.210m 6.202ms 5 5 100.00
hmac_test_hmac384_vectors 1.770m 6.646ms 5 5 100.00
hmac_test_hmac512_vectors 1.885m 18.985ms 5 5 100.00
hmac_stress_all 1.618h 69.347ms 50 50 100.00
V2 stress_all hmac_stress_all 1.618h 69.347ms 50 50 100.00
V2 alert_test hmac_alert_test 0.650s 22.154us 50 50 100.00
V2 intr_test hmac_intr_test 0.740s 209.490us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.980s 267.186us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.980s 267.186us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.000s 138.143us 5 5 100.00
hmac_csr_rw 0.970s 244.123us 20 20 100.00
hmac_csr_aliasing 8.880s 9.591ms 5 5 100.00
hmac_same_csr_outstanding 2.430s 562.659us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.000s 138.143us 5 5 100.00
hmac_csr_rw 0.970s 244.123us 20 20 100.00
hmac_csr_aliasing 8.880s 9.591ms 5 5 100.00
hmac_same_csr_outstanding 2.430s 562.659us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 0.980s 78.806us 5 5 100.00
hmac_tl_intg_err 4.490s 282.459us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.490s 282.459us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 16.850s 1.355ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.667h 67.461ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.52 95.26 97.33 100.00 94.12 98.12 97.97 99.85

Past Results