HMAC Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 14.280s 16.886ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.980s 506.343us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.940s 20.419us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.700s 1.406ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 8.600s 1.018ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 15.423m 352.160ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.940s 20.419us 20 20 100.00
hmac_csr_aliasing 8.600s 1.018ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.478m 59.809ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.928m 3.852ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 11.894m 108.911ms 5 5 100.00
hmac_test_sha384_vectors 42.510m 290.860ms 5 5 100.00
hmac_test_sha512_vectors 44.555m 1.726s 5 5 100.00
hmac_test_hmac256_vectors 1.226m 4.334ms 5 5 100.00
hmac_test_hmac384_vectors 1.422m 2.241ms 5 5 100.00
hmac_test_hmac512_vectors 2.091m 10.124ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.098m 1.212ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 18.697m 55.110ms 50 50 100.00
V2 error hmac_error 3.695m 10.666ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.746m 12.187ms 50 50 100.00
V2 save_and_restore hmac_smoke 14.280s 16.886ms 50 50 100.00
hmac_long_msg 3.478m 59.809ms 50 50 100.00
hmac_back_pressure 1.928m 3.852ms 50 50 100.00
hmac_datapath_stress 18.697m 55.110ms 50 50 100.00
hmac_burst_wr 1.098m 1.212ms 50 50 100.00
hmac_stress_all 1.350h 66.636ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 14.280s 16.886ms 50 50 100.00
hmac_long_msg 3.478m 59.809ms 50 50 100.00
hmac_back_pressure 1.928m 3.852ms 50 50 100.00
hmac_datapath_stress 18.697m 55.110ms 50 50 100.00
hmac_wipe_secret 2.746m 12.187ms 50 50 100.00
hmac_test_sha256_vectors 11.894m 108.911ms 5 5 100.00
hmac_test_sha384_vectors 42.510m 290.860ms 5 5 100.00
hmac_test_sha512_vectors 44.555m 1.726s 5 5 100.00
hmac_test_hmac256_vectors 1.226m 4.334ms 5 5 100.00
hmac_test_hmac384_vectors 1.422m 2.241ms 5 5 100.00
hmac_test_hmac512_vectors 2.091m 10.124ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 14.280s 16.886ms 50 50 100.00
hmac_long_msg 3.478m 59.809ms 50 50 100.00
hmac_back_pressure 1.928m 3.852ms 50 50 100.00
hmac_datapath_stress 18.697m 55.110ms 50 50 100.00
hmac_burst_wr 1.098m 1.212ms 50 50 100.00
hmac_error 3.695m 10.666ms 50 50 100.00
hmac_wipe_secret 2.746m 12.187ms 50 50 100.00
hmac_test_sha256_vectors 11.894m 108.911ms 5 5 100.00
hmac_test_sha384_vectors 42.510m 290.860ms 5 5 100.00
hmac_test_sha512_vectors 44.555m 1.726s 5 5 100.00
hmac_test_hmac256_vectors 1.226m 4.334ms 5 5 100.00
hmac_test_hmac384_vectors 1.422m 2.241ms 5 5 100.00
hmac_test_hmac512_vectors 2.091m 10.124ms 5 5 100.00
hmac_stress_all 1.350h 66.636ms 50 50 100.00
V2 stress_all hmac_stress_all 1.350h 66.636ms 50 50 100.00
V2 alert_test hmac_alert_test 0.680s 12.490us 50 50 100.00
V2 intr_test hmac_intr_test 0.690s 13.857us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.350s 984.994us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.350s 984.994us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.980s 506.343us 5 5 100.00
hmac_csr_rw 0.940s 20.419us 20 20 100.00
hmac_csr_aliasing 8.600s 1.018ms 5 5 100.00
hmac_same_csr_outstanding 2.360s 298.369us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.980s 506.343us 5 5 100.00
hmac_csr_rw 0.940s 20.419us 20 20 100.00
hmac_csr_aliasing 8.600s 1.018ms 5 5 100.00
hmac_same_csr_outstanding 2.360s 298.369us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.200s 167.155us 5 5 100.00
hmac_tl_intg_err 4.630s 290.369us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.630s 290.369us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 14.280s 16.886ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.529h 495.591ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.05 95.40 97.27 100.00 97.06 98.27 98.48 99.85

Past Results