HMAC Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.290s	1.350ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.010s	110.390us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	58.994us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.980s	1.052ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.830s	1.855ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.515m	168.690ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	58.994us	20	20	100.00
		hmac_csr_aliasing	8.830s	1.855ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.423m	176.158ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.832m	3.711ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.727m	194.110ms	5	5	100.00
		hmac_test_sha384_vectors	44.430m	832.344ms	5	5	100.00
		hmac_test_sha512_vectors	40.243m	149.046ms	5	5	100.00
		hmac_test_hmac256_vectors	1.352m	9.783ms	5	5	100.00
		hmac_test_hmac384_vectors	1.555m	24.906ms	5	5	100.00
		hmac_test_hmac512_vectors	2.278m	16.688ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.361m	19.716ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	29.225m	9.248ms	50	50	100.00
V2	error	hmac_error	5.513m	97.169ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.611m	25.642ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.290s	1.350ms	50	50	100.00
		hmac_long_msg	3.423m	176.158ms	50	50	100.00
		hmac_back_pressure	1.832m	3.711ms	50	50	100.00
		hmac_datapath_stress	29.225m	9.248ms	50	50	100.00
		hmac_burst_wr	1.361m	19.716ms	50	50	100.00
		hmac_stress_all	1.708h	117.001ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.290s	1.350ms	50	50	100.00
		hmac_long_msg	3.423m	176.158ms	50	50	100.00
		hmac_back_pressure	1.832m	3.711ms	50	50	100.00
		hmac_datapath_stress	29.225m	9.248ms	50	50	100.00
		hmac_wipe_secret	2.611m	25.642ms	50	50	100.00
		hmac_test_sha256_vectors	10.727m	194.110ms	5	5	100.00
		hmac_test_sha384_vectors	44.430m	832.344ms	5	5	100.00
		hmac_test_sha512_vectors	40.243m	149.046ms	5	5	100.00
		hmac_test_hmac256_vectors	1.352m	9.783ms	5	5	100.00
		hmac_test_hmac384_vectors	1.555m	24.906ms	5	5	100.00
		hmac_test_hmac512_vectors	2.278m	16.688ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.290s	1.350ms	50	50	100.00
		hmac_long_msg	3.423m	176.158ms	50	50	100.00
		hmac_back_pressure	1.832m	3.711ms	50	50	100.00
		hmac_datapath_stress	29.225m	9.248ms	50	50	100.00
		hmac_burst_wr	1.361m	19.716ms	50	50	100.00
		hmac_error	5.513m	97.169ms	50	50	100.00
		hmac_wipe_secret	2.611m	25.642ms	50	50	100.00
		hmac_test_sha256_vectors	10.727m	194.110ms	5	5	100.00
		hmac_test_sha384_vectors	44.430m	832.344ms	5	5	100.00
		hmac_test_sha512_vectors	40.243m	149.046ms	5	5	100.00
		hmac_test_hmac256_vectors	1.352m	9.783ms	5	5	100.00
		hmac_test_hmac384_vectors	1.555m	24.906ms	5	5	100.00
		hmac_test_hmac512_vectors	2.278m	16.688ms	5	5	100.00
		hmac_stress_all	1.708h	117.001ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.708h	117.001ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.630s	25.863us	50	50	100.00
V2	intr_test	hmac_intr_test	0.670s	22.300us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.660s	1.434ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.660s	1.434ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.010s	110.390us	5	5	100.00
		hmac_csr_rw	0.970s	58.994us	20	20	100.00
		hmac_csr_aliasing	8.830s	1.855ms	5	5	100.00
		hmac_same_csr_outstanding	2.390s	310.911us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.010s	110.390us	5	5	100.00
		hmac_csr_rw	0.970s	58.994us	20	20	100.00
		hmac_csr_aliasing	8.830s	1.855ms	5	5	100.00
		hmac_same_csr_outstanding	2.390s	310.911us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	0.980s	80.895us	5	5	100.00
		hmac_tl_intg_err	4.640s	331.533us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.640s	331.533us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.290s	1.350ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.704h	71.371ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			660	660	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.04	95.40	97.22	100.00	97.06	98.27	98.48	99.85

Past Results

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