HMAC Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.290s	1.311ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.010s	147.791us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.930s	523.222us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.020s	5.705ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.000s	9.672ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.077m	102.784ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.930s	523.222us	20	20	100.00
		hmac_csr_aliasing	9.000s	9.672ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.306m	10.344ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.935m	3.894ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.001m	51.666ms	5	5	100.00
		hmac_test_sha384_vectors	43.083m	849.109ms	5	5	100.00
		hmac_test_sha512_vectors	42.716m	489.421ms	5	5	100.00
		hmac_test_hmac256_vectors	1.297m	6.058ms	5	5	100.00
		hmac_test_hmac384_vectors	1.745m	13.603ms	5	5	100.00
		hmac_test_hmac512_vectors	1.512m	35.756ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.305m	6.060ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	34.745m	39.781ms	50	50	100.00
V2	error	hmac_error	4.244m	70.446ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.385m	50.479ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.290s	1.311ms	50	50	100.00
		hmac_long_msg	3.306m	10.344ms	50	50	100.00
		hmac_back_pressure	1.935m	3.894ms	50	50	100.00
		hmac_datapath_stress	34.745m	39.781ms	50	50	100.00
		hmac_burst_wr	1.305m	6.060ms	50	50	100.00
		hmac_stress_all	1.273h	68.729ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.290s	1.311ms	50	50	100.00
		hmac_long_msg	3.306m	10.344ms	50	50	100.00
		hmac_back_pressure	1.935m	3.894ms	50	50	100.00
		hmac_datapath_stress	34.745m	39.781ms	50	50	100.00
		hmac_wipe_secret	2.385m	50.479ms	50	50	100.00
		hmac_test_sha256_vectors	11.001m	51.666ms	5	5	100.00
		hmac_test_sha384_vectors	43.083m	849.109ms	5	5	100.00
		hmac_test_sha512_vectors	42.716m	489.421ms	5	5	100.00
		hmac_test_hmac256_vectors	1.297m	6.058ms	5	5	100.00
		hmac_test_hmac384_vectors	1.745m	13.603ms	5	5	100.00
		hmac_test_hmac512_vectors	1.512m	35.756ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.290s	1.311ms	50	50	100.00
		hmac_long_msg	3.306m	10.344ms	50	50	100.00
		hmac_back_pressure	1.935m	3.894ms	50	50	100.00
		hmac_datapath_stress	34.745m	39.781ms	50	50	100.00
		hmac_burst_wr	1.305m	6.060ms	50	50	100.00
		hmac_error	4.244m	70.446ms	50	50	100.00
		hmac_wipe_secret	2.385m	50.479ms	50	50	100.00
		hmac_test_sha256_vectors	11.001m	51.666ms	5	5	100.00
		hmac_test_sha384_vectors	43.083m	849.109ms	5	5	100.00
		hmac_test_sha512_vectors	42.716m	489.421ms	5	5	100.00
		hmac_test_hmac256_vectors	1.297m	6.058ms	5	5	100.00
		hmac_test_hmac384_vectors	1.745m	13.603ms	5	5	100.00
		hmac_test_hmac512_vectors	1.512m	35.756ms	5	5	100.00
		hmac_stress_all	1.273h	68.729ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.273h	68.729ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.700s	87.952us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	60.591us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.970s	107.884us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.970s	107.884us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.010s	147.791us	5	5	100.00
		hmac_csr_rw	0.930s	523.222us	20	20	100.00
		hmac_csr_aliasing	9.000s	9.672ms	5	5	100.00
		hmac_same_csr_outstanding	2.480s	168.268us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.010s	147.791us	5	5	100.00
		hmac_csr_rw	0.930s	523.222us	20	20	100.00
		hmac_csr_aliasing	9.000s	9.672ms	5	5	100.00
		hmac_same_csr_outstanding	2.480s	168.268us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	1.020s	521.303us	5	5	100.00
		hmac_tl_intg_err	4.430s	1.067ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.430s	1.067ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.290s	1.311ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.035h	116.143ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			660	660	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.46	95.40	97.22	100.00	100.00	98.27	98.48	99.85

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