HMAC Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	23.800s	1.037ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.020s	23.833us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.210s	30.475us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.060s	1.585ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.410s	301.933us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	20.744m	104.456ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.210s	30.475us	20	20	100.00
		hmac_csr_aliasing	7.410s	301.933us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.532m	3.551ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.206m	1.714ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	12.808m	145.401ms	5	5	100.00
		hmac_test_sha384_vectors	46.611m	859.948ms	5	5	100.00
		hmac_test_sha512_vectors	52.947m	226.522ms	5	5	100.00
		hmac_test_hmac256_vectors	1.330m	4.778ms	5	5	100.00
		hmac_test_hmac384_vectors	2.200m	39.722ms	5	5	100.00
		hmac_test_hmac512_vectors	2.523m	6.018ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.445m	12.526ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	26.956m	47.046ms	50	50	100.00
V2	error	hmac_error	4.474m	16.370ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.993m	9.799ms	50	50	100.00
V2	save_and_restore	hmac_smoke	23.800s	1.037ms	50	50	100.00
		hmac_long_msg	4.532m	3.551ms	50	50	100.00
		hmac_back_pressure	2.206m	1.714ms	50	50	100.00
		hmac_datapath_stress	26.956m	47.046ms	50	50	100.00
		hmac_burst_wr	1.445m	12.526ms	50	50	100.00
		hmac_stress_all	1.322h	24.818ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	23.800s	1.037ms	50	50	100.00
		hmac_long_msg	4.532m	3.551ms	50	50	100.00
		hmac_back_pressure	2.206m	1.714ms	50	50	100.00
		hmac_datapath_stress	26.956m	47.046ms	50	50	100.00
		hmac_wipe_secret	2.993m	9.799ms	50	50	100.00
		hmac_test_sha256_vectors	12.808m	145.401ms	5	5	100.00
		hmac_test_sha384_vectors	46.611m	859.948ms	5	5	100.00
		hmac_test_sha512_vectors	52.947m	226.522ms	5	5	100.00
		hmac_test_hmac256_vectors	1.330m	4.778ms	5	5	100.00
		hmac_test_hmac384_vectors	2.200m	39.722ms	5	5	100.00
		hmac_test_hmac512_vectors	2.523m	6.018ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	23.800s	1.037ms	50	50	100.00
		hmac_long_msg	4.532m	3.551ms	50	50	100.00
		hmac_back_pressure	2.206m	1.714ms	50	50	100.00
		hmac_datapath_stress	26.956m	47.046ms	50	50	100.00
		hmac_burst_wr	1.445m	12.526ms	50	50	100.00
		hmac_error	4.474m	16.370ms	50	50	100.00
		hmac_wipe_secret	2.993m	9.799ms	50	50	100.00
		hmac_test_sha256_vectors	12.808m	145.401ms	5	5	100.00
		hmac_test_sha384_vectors	46.611m	859.948ms	5	5	100.00
		hmac_test_sha512_vectors	52.947m	226.522ms	5	5	100.00
		hmac_test_hmac256_vectors	1.330m	4.778ms	5	5	100.00
		hmac_test_hmac384_vectors	2.200m	39.722ms	5	5	100.00
		hmac_test_hmac512_vectors	2.523m	6.018ms	5	5	100.00
		hmac_stress_all	1.322h	24.818ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.322h	24.818ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.940s	15.164us	50	50	100.00
V2	intr_test	hmac_intr_test	0.850s	18.627us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	45.560s		19	20	95.00
V2	tl_d_illegal_access	hmac_tl_errors	45.560s		19	20	95.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.020s	23.833us	5	5	100.00
		hmac_csr_rw	1.210s	30.475us	20	20	100.00
		hmac_csr_aliasing	7.410s	301.933us	5	5	100.00
		hmac_same_csr_outstanding	2.450s	45.918us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.020s	23.833us	5	5	100.00
		hmac_csr_rw	1.210s	30.475us	20	20	100.00
		hmac_csr_aliasing	7.410s	301.933us	5	5	100.00
		hmac_same_csr_outstanding	2.450s	45.918us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.490s	180.682us	5	5	100.00
		hmac_tl_intg_err	4.180s	573.888us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.180s	573.888us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	23.800s	1.037ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	12.375m	7.458ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			655	660	99.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	95.40	97.22	100.00	94.12	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 1.hmac_stress_all_with_rand_reset.48135587063402706664438500671706465979611056925248111542284649958932778382731
    Line 7446, in log /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1668175410 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1668175410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 3.hmac_stress_all_with_rand_reset.88082181212957770970380694895557747832959711217310105492030874679716314848436
    Line 7190, in log /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2295531724 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2295531724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 6.hmac_stress_all_with_rand_reset.114181109618123451063829113850492706905225387137738081596667958656815385401589
    Line 75872, in log /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7458140923 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 7458140923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 9.hmac_stress_all_with_rand_reset.111366564039880447257928962842686725276122053787798122387443333985186092727607
    Line 25288, in log /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10930356333 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 1000000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10930356333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 1 failures:

Test hmac_tl_errors has 1 failures.

9.hmac_tl_errors.92296680000710991231880573442515359479945895477187679896448729220002324020223
Log /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_tl_errors/latest/run.log

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  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 07:03 2024
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  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255