HMAC Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	22.740s	2.755ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.540s	125.738us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.540s	30.179us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	22.340s	15.065ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.620s	1.853ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.301m	539.505ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.540s	30.179us	20	20	100.00
		hmac_csr_aliasing	9.620s	1.853ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.197m	96.395ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.325m	14.096ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	12.397m	52.459ms	5	5	100.00
		hmac_test_sha384_vectors	44.563m	204.241ms	5	5	100.00
		hmac_test_sha512_vectors	51.943m	915.580ms	5	5	100.00
		hmac_test_hmac256_vectors	56.010s	8.926ms	5	5	100.00
		hmac_test_hmac384_vectors	1.658m	13.347ms	5	5	100.00
		hmac_test_hmac512_vectors	2.111m	22.446ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.564m	1.209ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	32.661m	32.335ms	50	50	100.00
V2	error	hmac_error	5.050m	77.120ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	3.232m	20.332ms	50	50	100.00
V2	save_and_restore	hmac_smoke	22.740s	2.755ms	50	50	100.00
		hmac_long_msg	4.197m	96.395ms	50	50	100.00
		hmac_back_pressure	2.325m	14.096ms	50	50	100.00
		hmac_datapath_stress	32.661m	32.335ms	50	50	100.00
		hmac_burst_wr	1.564m	1.209ms	50	50	100.00
		hmac_stress_all	1.690h	517.359ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	22.740s	2.755ms	50	50	100.00
		hmac_long_msg	4.197m	96.395ms	50	50	100.00
		hmac_back_pressure	2.325m	14.096ms	50	50	100.00
		hmac_datapath_stress	32.661m	32.335ms	50	50	100.00
		hmac_wipe_secret	3.232m	20.332ms	50	50	100.00
		hmac_test_sha256_vectors	12.397m	52.459ms	5	5	100.00
		hmac_test_sha384_vectors	44.563m	204.241ms	5	5	100.00
		hmac_test_sha512_vectors	51.943m	915.580ms	5	5	100.00
		hmac_test_hmac256_vectors	56.010s	8.926ms	5	5	100.00
		hmac_test_hmac384_vectors	1.658m	13.347ms	5	5	100.00
		hmac_test_hmac512_vectors	2.111m	22.446ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	22.740s	2.755ms	50	50	100.00
		hmac_long_msg	4.197m	96.395ms	50	50	100.00
		hmac_back_pressure	2.325m	14.096ms	50	50	100.00
		hmac_datapath_stress	32.661m	32.335ms	50	50	100.00
		hmac_burst_wr	1.564m	1.209ms	50	50	100.00
		hmac_error	5.050m	77.120ms	50	50	100.00
		hmac_wipe_secret	3.232m	20.332ms	50	50	100.00
		hmac_test_sha256_vectors	12.397m	52.459ms	5	5	100.00
		hmac_test_sha384_vectors	44.563m	204.241ms	5	5	100.00
		hmac_test_sha512_vectors	51.943m	915.580ms	5	5	100.00
		hmac_test_hmac256_vectors	56.010s	8.926ms	5	5	100.00
		hmac_test_hmac384_vectors	1.658m	13.347ms	5	5	100.00
		hmac_test_hmac512_vectors	2.111m	22.446ms	5	5	100.00
		hmac_stress_all	1.690h	517.359ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.690h	517.359ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.930s	39.733us	50	50	100.00
V2	intr_test	hmac_intr_test	0.990s	17.788us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	6.060s	770.807us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	6.060s	770.807us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.540s	125.738us	5	5	100.00
		hmac_csr_rw	1.540s	30.179us	20	20	100.00
		hmac_csr_aliasing	9.620s	1.853ms	5	5	100.00
		hmac_same_csr_outstanding	3.450s	448.615us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.540s	125.738us	5	5	100.00
		hmac_csr_rw	1.540s	30.179us	20	20	100.00
		hmac_csr_aliasing	9.620s	1.853ms	5	5	100.00
		hmac_same_csr_outstanding	3.450s	448.615us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	1.600s	82.367us	5	5	100.00
		hmac_tl_intg_err	6.030s	551.423us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.030s	551.423us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	22.740s	2.755ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	10.182m	16.141ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			657	660	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	95.26	97.27	100.00	97.06	98.12	97.97	99.85

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:80) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 0.hmac_stress_all_with_rand_reset.42685710785692012810690408533184045616761537873069710819373601375624218796459
    Line 28175, in log /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9823010926 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 9823010926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 4.hmac_stress_all_with_rand_reset.88122658025012106248751246589227187492070568268502909017600346944950207783938
    Line 1900, in log /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4703457058 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4703457058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 6.hmac_stress_all_with_rand_reset.79788437938439297577720951923791540416652154906932715234311498533555497207490
    Line 23167, in log /workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2190016975 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2190016975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `af2d1709f9`