HMAC Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	20.870s	705.077us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.110s	131.166us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.170s	492.746us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	12.970s	1.710ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.470s	2.278ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	15.168m	1.175s	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.170s	492.746us	20	20	100.00
		hmac_csr_aliasing	8.470s	2.278ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.273m	21.527ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.141m	2.092ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.998m	36.784ms	5	5	100.00
		hmac_test_sha384_vectors	48.109m	866.397ms	5	5	100.00
		hmac_test_sha512_vectors	45.861m	863.973ms	5	5	100.00
		hmac_test_hmac256_vectors	1.401m	8.795ms	5	5	100.00
		hmac_test_hmac384_vectors	1.705m	26.319ms	5	5	100.00
		hmac_test_hmac512_vectors	2.382m	83.818ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.616m	5.387ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	24.773m	45.271ms	50	50	100.00
V2	error	hmac_error	4.833m	68.915ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	3.179m	12.592ms	50	50	100.00
V2	save_and_restore	hmac_smoke	20.870s	705.077us	50	50	100.00
		hmac_long_msg	4.273m	21.527ms	50	50	100.00
		hmac_back_pressure	2.141m	2.092ms	50	50	100.00
		hmac_datapath_stress	24.773m	45.271ms	50	50	100.00
		hmac_burst_wr	1.616m	5.387ms	50	50	100.00
		hmac_stress_all	1.668h	365.962ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	20.870s	705.077us	50	50	100.00
		hmac_long_msg	4.273m	21.527ms	50	50	100.00
		hmac_back_pressure	2.141m	2.092ms	50	50	100.00
		hmac_datapath_stress	24.773m	45.271ms	50	50	100.00
		hmac_wipe_secret	3.179m	12.592ms	50	50	100.00
		hmac_test_sha256_vectors	10.998m	36.784ms	5	5	100.00
		hmac_test_sha384_vectors	48.109m	866.397ms	5	5	100.00
		hmac_test_sha512_vectors	45.861m	863.973ms	5	5	100.00
		hmac_test_hmac256_vectors	1.401m	8.795ms	5	5	100.00
		hmac_test_hmac384_vectors	1.705m	26.319ms	5	5	100.00
		hmac_test_hmac512_vectors	2.382m	83.818ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	20.870s	705.077us	50	50	100.00
		hmac_long_msg	4.273m	21.527ms	50	50	100.00
		hmac_back_pressure	2.141m	2.092ms	50	50	100.00
		hmac_datapath_stress	24.773m	45.271ms	50	50	100.00
		hmac_burst_wr	1.616m	5.387ms	50	50	100.00
		hmac_error	4.833m	68.915ms	50	50	100.00
		hmac_wipe_secret	3.179m	12.592ms	50	50	100.00
		hmac_test_sha256_vectors	10.998m	36.784ms	5	5	100.00
		hmac_test_sha384_vectors	48.109m	866.397ms	5	5	100.00
		hmac_test_sha512_vectors	45.861m	863.973ms	5	5	100.00
		hmac_test_hmac256_vectors	1.401m	8.795ms	5	5	100.00
		hmac_test_hmac384_vectors	1.705m	26.319ms	5	5	100.00
		hmac_test_hmac512_vectors	2.382m	83.818ms	5	5	100.00
		hmac_stress_all	1.668h	365.962ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.668h	365.962ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.910s	12.775us	50	50	100.00
V2	intr_test	hmac_intr_test	0.880s	29.247us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.970s	311.683us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.970s	311.683us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.110s	131.166us	5	5	100.00
		hmac_csr_rw	1.170s	492.746us	20	20	100.00
		hmac_csr_aliasing	8.470s	2.278ms	5	5	100.00
		hmac_same_csr_outstanding	2.490s	48.224us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.110s	131.166us	5	5	100.00
		hmac_csr_rw	1.170s	492.746us	20	20	100.00
		hmac_csr_aliasing	8.470s	2.278ms	5	5	100.00
		hmac_same_csr_outstanding	2.490s	48.224us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	1.220s	191.396us	5	5	100.00
		hmac_tl_intg_err	4.490s	356.099us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.490s	356.099us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	20.870s	705.077us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.563m	5.259ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			656	660	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.45	95.40	97.17	100.00	100.00	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:80) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 1.hmac_stress_all_with_rand_reset.5165400650338877559397636776893075454600917934401121557742178458961509126721
    Line 9663, in log /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13537806323 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 13537806323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 3.hmac_stress_all_with_rand_reset.9616500166240781199963949770910117768066955940241950780128610907476011326798
    Line 18620, in log /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3853534736 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3853534736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 6.hmac_stress_all_with_rand_reset.83441051372657943944836511271896012249246016290259028861001630957531387582244
    Line 11179, in log /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20406315455 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 20406315455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 7.hmac_stress_all_with_rand_reset.25091461862877911020573947940042030203970925549445716679658023998319355977636
    Line 13204, in log /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15268626409 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 15268626409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `372a6306e0`