25b1acbf68| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 22.360s | 1.350ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.950s | 41.386us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 38.679s | 19 | 20 | 95.00 | |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 14.610s | 1.064ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 7.830s | 7.341ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 15.290m | 107.671ms | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 38.679s | 19 | 20 | 95.00 | |
| hmac_csr_aliasing | 7.830s | 7.341ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 103 | 105 | 98.10 | |||
| V2 | long_msg | hmac_long_msg | 3.880m | 3.435ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.870m | 17.585ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha256_vectors | 11.892m | 52.658ms | 5 | 5 | 100.00 |
| hmac_test_sha384_vectors | 47.581m | 1.234s | 5 | 5 | 100.00 | ||
| hmac_test_sha512_vectors | 55.216m | 947.214ms | 5 | 5 | 100.00 | ||
| hmac_test_hmac256_vectors | 1.404m | 26.137ms | 5 | 5 | 100.00 | ||
| hmac_test_hmac384_vectors | 1.616m | 58.358ms | 5 | 5 | 100.00 | ||
| hmac_test_hmac512_vectors | 2.487m | 16.701ms | 5 | 5 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.805m | 11.492ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 24.491m | 42.776ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.462m | 18.818ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 2.987m | 40.329ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | hmac_smoke | 22.360s | 1.350ms | 50 | 50 | 100.00 |
| hmac_long_msg | 3.880m | 3.435ms | 50 | 50 | 100.00 | ||
| hmac_back_pressure | 1.870m | 17.585ms | 50 | 50 | 100.00 | ||
| hmac_datapath_stress | 24.491m | 42.776ms | 50 | 50 | 100.00 | ||
| hmac_burst_wr | 1.805m | 11.492ms | 50 | 50 | 100.00 | ||
| hmac_stress_all | 1.005h | 128.627ms | 50 | 50 | 100.00 | ||
| V2 | fifo_empty_status_interrupt | hmac_smoke | 22.360s | 1.350ms | 50 | 50 | 100.00 |
| hmac_long_msg | 3.880m | 3.435ms | 50 | 50 | 100.00 | ||
| hmac_back_pressure | 1.870m | 17.585ms | 50 | 50 | 100.00 | ||
| hmac_datapath_stress | 24.491m | 42.776ms | 50 | 50 | 100.00 | ||
| hmac_wipe_secret | 2.987m | 40.329ms | 50 | 50 | 100.00 | ||
| hmac_test_sha256_vectors | 11.892m | 52.658ms | 5 | 5 | 100.00 | ||
| hmac_test_sha384_vectors | 47.581m | 1.234s | 5 | 5 | 100.00 | ||
| hmac_test_sha512_vectors | 55.216m | 947.214ms | 5 | 5 | 100.00 | ||
| hmac_test_hmac256_vectors | 1.404m | 26.137ms | 5 | 5 | 100.00 | ||
| hmac_test_hmac384_vectors | 1.616m | 58.358ms | 5 | 5 | 100.00 | ||
| hmac_test_hmac512_vectors | 2.487m | 16.701ms | 5 | 5 | 100.00 | ||
| V2 | wide_digest_configurable_key_length | hmac_smoke | 22.360s | 1.350ms | 50 | 50 | 100.00 |
| hmac_long_msg | 3.880m | 3.435ms | 50 | 50 | 100.00 | ||
| hmac_back_pressure | 1.870m | 17.585ms | 50 | 50 | 100.00 | ||
| hmac_datapath_stress | 24.491m | 42.776ms | 50 | 50 | 100.00 | ||
| hmac_burst_wr | 1.805m | 11.492ms | 50 | 50 | 100.00 | ||
| hmac_error | 4.462m | 18.818ms | 50 | 50 | 100.00 | ||
| hmac_wipe_secret | 2.987m | 40.329ms | 50 | 50 | 100.00 | ||
| hmac_test_sha256_vectors | 11.892m | 52.658ms | 5 | 5 | 100.00 | ||
| hmac_test_sha384_vectors | 47.581m | 1.234s | 5 | 5 | 100.00 | ||
| hmac_test_sha512_vectors | 55.216m | 947.214ms | 5 | 5 | 100.00 | ||
| hmac_test_hmac256_vectors | 1.404m | 26.137ms | 5 | 5 | 100.00 | ||
| hmac_test_hmac384_vectors | 1.616m | 58.358ms | 5 | 5 | 100.00 | ||
| hmac_test_hmac512_vectors | 2.487m | 16.701ms | 5 | 5 | 100.00 | ||
| hmac_stress_all | 1.005h | 128.627ms | 50 | 50 | 100.00 | ||
| V2 | stress_all | hmac_stress_all | 1.005h | 128.627ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.970s | 124.996us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 49.642s | 47 | 50 | 94.00 | |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 49.701s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | hmac_tl_errors | 49.701s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.950s | 41.386us | 5 | 5 | 100.00 |
| hmac_csr_rw | 38.679s | 19 | 20 | 95.00 | |||
| hmac_csr_aliasing | 7.830s | 7.341ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 49.578s | 19 | 20 | 95.00 | |||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.950s | 41.386us | 5 | 5 | 100.00 |
| hmac_csr_rw | 38.679s | 19 | 20 | 95.00 | |||
| hmac_csr_aliasing | 7.830s | 7.341ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 49.578s | 19 | 20 | 95.00 | |||
| V2 | TOTAL | 514 | 520 | 98.85 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.680s | 111.171us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 49.674s | 18 | 20 | 90.00 | |||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 49.674s | 18 | 20 | 90.00 | |
| V2S | TOTAL | 23 | 25 | 92.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 22.360s | 1.350ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 6.370m | 109.921ms | 2 | 10 | 20.00 |
| V3 | TOTAL | 2 | 10 | 20.00 | |||
| TOTAL | 642 | 660 | 97.27 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 4 | 66.67 |
| V2 | 17 | 17 | 14 | 82.35 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.61 | 95.40 | 97.17 | 100.00 | 94.12 | 98.27 | 98.48 | 99.85 |
Job returned non-zero exit code has 10 failures:
Test hmac_csr_rw has 1 failures.
14.hmac_csr_rw.6722755595095458817272240880501681746572227273860612953406394964997459441668
Log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 13:11 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test hmac_tl_errors has 2 failures.
15.hmac_tl_errors.82386612527947766928007571402082832045035111969877026421561580204536902453757
Log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_tl_errors/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 13:11 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
19.hmac_tl_errors.87740942977150145035832790145430121564753573252772163342656729492589998038935
Log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_tl_errors/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 13:11 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test hmac_tl_intg_err has 2 failures.
15.hmac_tl_intg_err.54106016506747888589005339463090645106482522707187601365580229269083843036263
Log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_tl_intg_err/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 13:11 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
19.hmac_tl_intg_err.88001912303927448633701729975458714743579974052978354381071205061304767132791
Log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_tl_intg_err/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 13:11 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test hmac_intr_test has 3 failures.
15.hmac_intr_test.64468438563038119222070493008893283257588645865261422484866651320785265567269
Log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 13:11 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
18.hmac_intr_test.80219421612595994754178372780107481264120380209288496734673851056407521957091
Log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 13:11 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
... and 1 more failures.
Test hmac_same_csr_outstanding has 1 failures.
15.hmac_same_csr_outstanding.103813635136614916280895698238971270742417406985675320749700064128794397509211
Log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 13:11 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
... and 1 more tests.
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 4 failures:
1.hmac_stress_all_with_rand_reset.55197711969955261491330486361787687773554118051228144509357699313337026630702
Line 5534, in log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1935500412 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1935500412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.hmac_stress_all_with_rand_reset.64121477715216686269054184970225020416403163057159262839704769013637247239133
Line 2231, in log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2417367618 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2417367618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:
2.hmac_stress_all_with_rand_reset.89176480719550476229417506977832361725697063243051523491372450752632729184592
Line 3721, in log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11484277110 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 11484277110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.hmac_stress_all_with_rand_reset.23077808787577394292996669717996649078259292244794484572020519122003725363799
Line 29546, in log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 109921338908 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 109921338908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
0.hmac_stress_all_with_rand_reset.25543698920600363752886320186032219678004821672276813038673558060955760699358
Line 69, in log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13130184 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13130184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_base_vseq.sv:80) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
9.hmac_stress_all_with_rand_reset.57839862587376438878092541166972113718851478204464315781973160070732363897699
Line 22395, in log /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 41736699392 ps: (hmac_base_vseq.sv:80) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 41736699392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---