748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.357m | 9.468ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 44.040s | 1.629ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.690s | 42.841us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.730s | 55.506us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.960s | 575.471us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.260s | 137.097us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.300s | 80.398us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.730s | 55.506us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.260s | 137.097us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 154 | 155 | 99.35 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.160s | 176.878us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 54.652m | 55.294ms | 32 | 50 | 64.00 |
| V2 | host_perf | i2c_host_perf | 36.671m | 51.394ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.680s | 19.281us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 13.794m | 25.548ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 18.257m | 6.909ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.190s | 157.750us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 32.260s | 2.456ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 14.870s | 252.559us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.372m | 13.544ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 54.170s | 4.865ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 5.184m | 11.874ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 4.207m | 2.850ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 10.290s | 1.906ms | 50 | 50 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 3.700s | 858.685us | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 56.533m | 41.622ms | 45 | 50 | 90.00 |
| V2 | target_perf | i2c_target_perf | 5.970s | 3.866ms | 50 | 50 | 100.00 |
| V2 | target_fifo_overflow | i2c_target_tx_ovf | 4.209m | 4.353ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.426m | 8.522ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.270s | 2.104ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.209m | 10.088ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.494m | 10.154ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 35.985m | 39.149ms | 47 | 50 | 94.00 |
| i2c_target_stress_rd | 1.426m | 8.522ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 24.235m | 25.121ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.750s | 8.421ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 39.487m | 15.301ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.460s | 1.800ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.130s | 2.556ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.650s | 15.008us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.700s | 45.756us | 49 | 50 | 98.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.540s | 141.854us | 19 | 20 | 95.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.540s | 141.854us | 19 | 20 | 95.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.690s | 42.841us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.730s | 55.506us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.260s | 137.097us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.020s | 46.023us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.690s | 42.841us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.730s | 55.506us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.260s | 137.097us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.020s | 46.023us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1457 | 1492 | 97.65 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.780s | 112.407us | 19 | 20 | 95.00 |
| i2c_sec_cm | 0.910s | 124.245us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.780s | 112.407us | 19 | 20 | 95.00 |
| V2S | TOTAL | 24 | 25 | 96.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 15.112m | 78.675ms | 2 | 50 | 4.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 12.237m | 8.821ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 2 | 100 | 2.00 | |||
| TOTAL | 1637 | 1772 | 92.38 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 32 | 32 | 24 | 75.00 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.35 | 99.07 | 96.59 | 100.00 | 94.78 | 98.13 | 100.00 | 92.86 |
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 84 failures:
0.i2c_host_stress_all.65738817520321499532053307978923375472733154813050179951524815443328716384667
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job ID: smart:0539b086-30a5-4fdb-8afe-b6f973b840d6
4.i2c_host_stress_all.72447819642700018054198364240379650405046469780063339020266031026746042950441
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
Job ID: smart:4b64f7ef-d409-45c9-92e7-d16645e02c2c
... and 16 more failures.
0.i2c_target_stretch.47634137541914337596906070510563214486047327185888203222734269854286974679417
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
Job ID: smart:2ea0e885-c294-4560-9465-c9f9f526c206
10.i2c_target_stretch.49145508705374986601685136182805661744541886472362851089345346678568137925831
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stretch/latest/run.log
Job ID: smart:f86836d9-a9e0-4adc-b863-318f056365bc
... and 3 more failures.
0.i2c_host_stress_all_with_rand_reset.105810679266405776496358200312929096360850118313467298270399862365771195135863
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e99de979-d0cd-4eea-90a1-3c467384a63b
1.i2c_host_stress_all_with_rand_reset.59986904458068189917613975346592547734952452646499085807570884600884398135727
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:50466c9d-81a4-4030-9049-4944041c61d8
... and 43 more failures.
1.i2c_target_stress_all.66397334121941120210083307952720315626543643834888822030932082587612925958166
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
Job ID: smart:e195a6aa-9aca-4dfd-b854-f0681439c0bf
8.i2c_target_stress_all.68505136146511727959942184266620870036372618744210011381677576124944763496856
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
Job ID: smart:112e23aa-fcee-4786-a1e6-d4b161b6f2bc
... and 3 more failures.
4.i2c_target_stress_wr.23720604624811190153996285989533806231190255764462766681243952314015933670388
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_wr/latest/run.log
Job ID: smart:5e1bbdca-0145-4fc3-8678-46de461734b9
12.i2c_target_stress_wr.70469714503592695206588038644551499237677536901024639959917648637779948947049
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_wr/latest/run.log
Job ID: smart:1a349bd3-56b8-479e-9665-584b99bdd06b
... and 1 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 15 failures:
0.i2c_target_stress_all_with_rand_reset.23408478689680922222451428620933506588048813739953072027783982224719085575980
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 829748047 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 829748047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.86011476229629973429700505134379826327799735388460594096924861887566399728823
Line 363, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 62091129939 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 62091129939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 10 failures:
14.i2c_target_stress_all_with_rand_reset.107510078765920495830445589811058052384099186194499103021258214416319653609766
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 900044681 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x715a8f94) == 0x0
UVM_INFO @ 900044681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stress_all_with_rand_reset.33899697918444170246614958267154413218981373974576817867522737013509309641097
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3921035324 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xc8058c14) == 0x0
UVM_INFO @ 3921035324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 7 failures:
3.i2c_target_stress_all_with_rand_reset.59725625872844900665375467551804414792947233743046495972633367038824662924963
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 873217869 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 10 [0xa])
UVM_INFO @ 873217869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.89243244785746592149352414794958141042571326024098980035600767562356530799259
Line 416, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9463413087 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 5 [0x5])
UVM_INFO @ 9463413087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 6 failures:
4.i2c_target_stress_all_with_rand_reset.85782506577873981782254832086785798100047699118978347528508874639797759154680
Line 375, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8820796153 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (156 [0x9c] vs 58 [0x3a])
UVM_INFO @ 8820796153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all_with_rand_reset.64514755501473873612879698957431004144947959447478860166250148151481443984030
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 678428819 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (244 [0xf4] vs 245 [0xf5])
UVM_INFO @ 678428819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:
Test i2c_same_csr_outstanding has 1 failures.
10.i2c_same_csr_outstanding.66890550751696597746609640535684807505282901576473215280602920690619587351022
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/10.i2c_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410795502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_outstanding.2410795502
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test i2c_csr_mem_rw_with_rand_reset has 1 failures.
13.i2c_csr_mem_rw_with_rand_reset.46117960433957147663353481319930086475120813220483184179439308808201315711171
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837267139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1837267139
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test i2c_tl_intg_err has 1 failures.
17.i2c_tl_intg_err.15906896728489408050949416824266586231296903254678413288449735897098129643132
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/17.i2c_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165001340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3165001340
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test i2c_tl_errors has 1 failures.
19.i2c_tl_errors.73220815868141645136098476633775776854227857072364748743410920918909327354940
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_tl_errors/latest/run.log
[make]: simulate
cd /workspace/19.i2c_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991776316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3991776316
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test i2c_intr_test has 1 failures.
40.i2c_intr_test.22333465519642542371324665476208888917346289400725398652031420312752964822048
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_intr_test/latest/run.log
[make]: simulate
cd /workspace/40.i2c_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772413984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1772413984
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
UVM_ERROR (i2c_monitor.sv:448) monitor [monitor] ack_stop detected has 3 failures:
6.i2c_target_stress_all_with_rand_reset.105426956722572897866567756671728369066566064646479512668513986738522833699027
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 141879184 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 141879184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stress_all_with_rand_reset.48031964269214870083370813187114510851394706950549742413311338814415606590014
Line 377, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8013806903 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 8013806903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:698) scoreboard [scoreboard] has 1 failures:
2.i2c_host_stress_all_with_rand_reset.111360622133831625681451590638568968200260836055728380777060815490651247908757
Line 291, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1304317964 ps: (i2c_scoreboard.sv:698) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
UVM_ERROR (i2c_host_fifo_overflow_vseq.sv:64) [i2c_host_fifo_overflow_vseq] Check failed cnt_fmt_overflow > * (* [*] vs * [*]) has 1 failures:
6.i2c_host_stress_all_with_rand_reset.79226749070052709848424490247222105911541905749932921015611605473862245850135
Line 18114, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 78674520440 ps: (i2c_host_fifo_overflow_vseq.sv:64) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_overflow_vseq] Check failed cnt_fmt_overflow > 0 (0 [0x0] vs 0 [0x0])
UVM_INFO @ 78674520440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:56) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
8.i2c_host_stress_all_with_rand_reset.50494351008185226751628664114468783001427352314086627503368116708949603155418
Line 1049, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 816885377 ps: (i2c_host_fifo_watermark_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 816885377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_i' has 1 failures:
44.i2c_target_stress_all_with_rand_reset.66419007023556856807715232277168055313304211462228274516281740676788292259263
Line 461, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 14862266702 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 14862266702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:791) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
49.i2c_target_stress_all_with_rand_reset.15543851878365913244872682368614640514345854700191335150404624207217153054790
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 166083643 ps: (i2c_scoreboard.sv:791) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 101 [0x65])
UVM_INFO @ 166083643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---