c187a82ee8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.807m | 4.899ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 42.628m | 100.000ms | 14 | 50 | 28.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.760s | 67.916us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.790s | 74.810us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.820s | 481.230us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.540s | 72.397us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.300s | 144.471us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.790s | 74.810us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.540s | 72.397us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 119 | 155 | 76.77 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.100s | 47.445us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 50.582m | 57.371ms | 41 | 50 | 82.00 |
| V2 | host_perf | i2c_host_perf | 34.922m | 71.629ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.710s | 28.805us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.759m | 11.160ms | 46 | 50 | 92.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 4.149m | 3.899ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.180s | 139.909us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 31.810s | 620.551us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.770s | 231.135us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.509m | 51.548ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 42.170s | 905.196us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 3.768m | 4.886ms | 48 | 50 | 96.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 9.360s | 8.339ms | 41 | 50 | 82.00 |
| V2 | target_glitch | i2c_target_glitch | 13.040s | 3.295ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 13.673m | 39.835ms | 24 | 50 | 48.00 |
| V2 | target_perf | i2c_target_perf | 5.580s | 3.285ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 39.449m | 100.000ms | 21 | 50 | 42.00 |
| i2c_target_intr_smoke | 7.450s | 1.442ms | 39 | 50 | 78.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.300m | 10.099ms | 40 | 50 | 80.00 |
| i2c_target_fifo_reset_tx | 1.931m | 10.096ms | 43 | 50 | 86.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 42.906m | 63.769ms | 42 | 50 | 84.00 |
| i2c_target_stress_rd | 39.449m | 100.000ms | 21 | 50 | 42.00 | ||
| i2c_target_intr_stress_wr | 7.502m | 21.605ms | 40 | 50 | 80.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.800s | 7.675ms | 43 | 50 | 86.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 45.104m | 18.296ms | 40 | 50 | 80.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.540s | 5.756ms | 43 | 50 | 86.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.610s | 3.688ms | 42 | 50 | 84.00 |
| V2 | alert_test | i2c_alert_test | 0.710s | 26.426us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.750s | 21.704us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.310s | 182.232us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.310s | 182.232us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.760s | 67.916us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.790s | 74.810us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.540s | 72.397us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.090s | 90.340us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.760s | 67.916us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.790s | 74.810us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.540s | 72.397us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.090s | 90.340us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1233 | 1392 | 88.58 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.130s | 405.883us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.990s | 74.217us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.130s | 405.883us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.380m | 60.712ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 11.188m | 100.350ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 1377 | 1672 | 82.36 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 31 | 30 | 13 | 41.94 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.64 | 98.70 | 96.00 | 100.00 | 93.04 | 97.21 | 100.00 | 91.49 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 70 failures:
Test i2c_target_timeout has 3 failures.
0.i2c_target_timeout.53743590291173658023317366022735599545822741174293190213451139338646964767982
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_timeout/latest/run.log
UVM_ERROR @ 102470496 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 102470496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_timeout.81760910801054407596036800225303943503889106174220275961097078929784978897746
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_timeout/latest/run.log
UVM_ERROR @ 46963817 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 46963817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test i2c_target_fifo_reset_acq has 10 failures.
0.i2c_target_fifo_reset_acq.104995093826205019851492067755663719967041523013916927238543850751853576546924
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_fifo_reset_acq/latest/run.log
UVM_ERROR @ 146815680 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 146815680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_fifo_reset_acq.90856746380891565946112454435419687480466739673190930653496350176708482017586
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_fifo_reset_acq/latest/run.log
UVM_ERROR @ 62395210 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 62395210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test i2c_target_stress_wr has 7 failures.
2.i2c_target_stress_wr.68398146083753551358251508493467559370358076931596106967801869527397187331424
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_wr/latest/run.log
UVM_ERROR @ 7263121 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 7263121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_wr.77745080053420883073151821279459626981998556249025275645872886806691409212004
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_wr/latest/run.log
UVM_ERROR @ 12905303 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 12905303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test i2c_target_fifo_reset_tx has 2 failures.
5.i2c_target_fifo_reset_tx.71923494939746099072562500072113552573317108346388587560596947696127145261934
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_fifo_reset_tx/latest/run.log
UVM_ERROR @ 75794482 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 75794482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.i2c_target_fifo_reset_tx.15443356578196849842362003472449962229928890986758105430505531546042730797172
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_fifo_reset_tx/latest/run.log
UVM_ERROR @ 79653600 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 79653600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_bad_addr has 1 failures.
6.i2c_target_bad_addr.56437280079563636755686961650456817592754805297680389686339742286381420622706
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_bad_addr/latest/run.log
UVM_ERROR @ 11990728 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 11990728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more tests.
UVM_ERROR (i2c_scoreboard.sv:773) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 58 failures:
0.i2c_target_smoke.112167393293833925099771004871860134496376099545451914568572461190099848282057
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_smoke/latest/run.log
UVM_ERROR @ 165105435 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 165105435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_smoke.12239559734761053684166118143895168470158149300868825683296298523939352806664
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_smoke/latest/run.log
UVM_ERROR @ 58011466 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 58011466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
1.i2c_target_bad_addr.101252642161718289338249064139826714074874292663859741031200461271990334696192
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_bad_addr/latest/run.log
UVM_ERROR @ 68103826 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 68103826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_bad_addr.100339822980698982327843457709549836179524785240466738515364733636622169821119
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_bad_addr/latest/run.log
UVM_ERROR @ 59677991 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 59677991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
2.i2c_target_hrst.15359432238004385818812465883351755888334188956760986328312702179766290382895
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_ERROR @ 218816290 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 218816290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_hrst.17703734407514378055472521249956447708600771505544688404950357493143277645298
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_hrst/latest/run.log
UVM_ERROR @ 365243458 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 365243458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
5.i2c_target_stress_rd.84338272449856000099505532768082508890111163502359064606627155028554097118744
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_rd/latest/run.log
UVM_ERROR @ 599801287 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 599801287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_rd.77133916920541261852540482893418521209373969213313111376529747251011329153926
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_rd/latest/run.log
UVM_ERROR @ 131654179 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 131654179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
9.i2c_target_stress_all_with_rand_reset.64124868393826206506835895617123343939581984700964096384180089098419350127656
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28565550 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 28565550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.i2c_target_stress_all_with_rand_reset.84987680549626293723050615584289054854360611029626234960945173741709008887358
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 110527952 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 110527952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:827) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 54 failures:
0.i2c_host_stress_all_with_rand_reset.93129690351833699782292753714659135049166252708270445101219491532682573708721
Line 3021, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3034944976 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3034944976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.36382654157161367351484965447845555546867098307291120417114325156145306447922
Line 2982, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3949245738 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3949245738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 44 more failures.
2.i2c_target_stress_all_with_rand_reset.73242153853113038081871501153835554300335402825507364490697710507016309497265
Line 302, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7704840774 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7704840774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.75349555789894461155388483670694801769136987347779796287418063180891416047789
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1135973964 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1135973964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 34 failures:
1.i2c_target_smoke.31783960031645442698745079792938550092439441930908796952679785561946833639806
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_smoke/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_smoke.73311331120116610104141938759639628541269816193968722466330088702285945994176
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_smoke/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
7.i2c_target_stress_rd.70396872745865953830762175818974302688757018870423308666596898467544660012190
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_rd/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_stress_rd.52853877277637711810212568552543355697747083318683233770846350001482790923879
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_rd/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
33.i2c_target_fifo_reset_tx.70932520627440101366359656877329662358473977927148067683518511434433486176288
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_fifo_reset_tx/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 33 failures:
Test i2c_target_stress_rd has 11 failures.
0.i2c_target_stress_rd.41947264142592433393018941526310316873257015111962783771753167490635994636037
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_rd/latest/run.log
Job ID: smart:da4401c0-b635-46cc-8607-bde18efe3ee8
8.i2c_target_stress_rd.30518262441845405168262780295974181638974704633187447087686161834847157981315
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_rd/latest/run.log
Job ID: smart:558e8864-f4e0-44e4-893e-cab8619befa0
... and 9 more failures.
Test i2c_target_smoke has 6 failures.
2.i2c_target_smoke.103208892748956624230875052892045280034393519658016200668295275900020656613658
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_smoke/latest/run.log
Job ID: smart:fc6902da-4301-4c43-a5fe-f8f504f86ca4
8.i2c_target_smoke.80248229379656741510533740601563840105317461738384876354935881653738044224203
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_smoke/latest/run.log
Job ID: smart:c42fb556-2d16-4a2a-b032-c12822a07c30
... and 4 more failures.
Test i2c_target_stretch has 2 failures.
5.i2c_target_stretch.32101804294024189840102924842316613084555158850632538947395745971062682751137
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
Job ID: smart:13e9f107-f955-4b3f-83e9-e9abed038041
8.i2c_target_stretch.47291062832735380495904354224880604430464650464543710812905538409241576327559
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stretch/latest/run.log
Job ID: smart:bc45ec57-d4d1-4cde-8d01-83924a3a5ba8
Test i2c_host_stress_all_with_rand_reset has 4 failures.
6.i2c_host_stress_all_with_rand_reset.61200243405124122676342379240487664060488513064725818925259786236957100119884
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:04aa70a4-de70-4143-98e5-c0f7a25e9753
15.i2c_host_stress_all_with_rand_reset.107012597295265020991701970703858172647697511839911982740921844523359859167374
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:c484b85c-0422-442e-94ca-4acf0773f076
... and 2 more failures.
Test i2c_host_stress_all has 6 failures.
10.i2c_host_stress_all.69092708149117919520408078043485940518145559589425532929211275783293963584685
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
Job ID: smart:c298f640-bd62-405d-a1ed-56908ce0263c
19.i2c_host_stress_all.83807620205687464773686839427092978874600244837745543109480345738054651850651
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
Job ID: smart:ee958c34-a005-462d-9dbe-1e860f758a13
... and 4 more failures.
... and 3 more tests.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 15 failures:
0.i2c_target_stress_all_with_rand_reset.30484664086275752831277133487488712812019595741248591595638617926544588943485
Line 415, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10181618874 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 7 [0x7])
UVM_INFO @ 10181618874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.33535080206862347456195757799790166348241568338889658130563325284146215486294
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1997438394 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 6 [0x6])
UVM_INFO @ 1997438394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:55) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 7 failures:
2.i2c_host_stress_all.100653806266127803456735662136096455545166699193001873268456526197505245814322
Line 7354, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 33566803264 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 33566803264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_host_stress_all.27506387239384819535122842947725659416904429646974249358441899298492964442398
Line 514, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 287513330 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 287513330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
10.i2c_host_fifo_watermark.58842480665254775920487888733961069673758736605430181854818765280491622054214
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_fifo_watermark/latest/run.log
UVM_ERROR @ 176507438 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 176507438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_host_fifo_watermark.39483420716379528809835780697211747739346088244466043615642146529369862211444
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_fifo_watermark/latest/run.log
UVM_ERROR @ 133769247 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 133769247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Offending 'scl_i' has 4 failures:
3.i2c_target_stress_all_with_rand_reset.86655138289812353052081642995388276072114023645352713429861512631663685679692
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 12597338525 ps: (i2c_fsm.sv:1356) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 12597338525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_stress_all_with_rand_reset.9209046609486328152821817454266894441153836264373765087734519962658240783536
Line 389, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 39201891210 ps: (i2c_fsm.sv:1356) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 39201891210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 4 failures:
22.i2c_target_stress_all_with_rand_reset.30381958624640217874978038324180674427927363930311908468043117344747926781355
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 174570834 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x84eff894) == 0x0
UVM_INFO @ 174570834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.i2c_target_stress_all_with_rand_reset.38537769658715839031844857374809869342912774287360651276840892293505404288508
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2186885781 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xf83b6b14) == 0x0
UVM_INFO @ 2186885781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred! has 3 failures:
6.i2c_target_stress_all.94722097225568415029129808525904270417634314600597071774526226387085266839105
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 14083740647 ps: (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 14083740647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_stress_all.31272963184868074659268024510011362664702662094619248628042489287639561956060
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 66510293665 ps: (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 66510293665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_base_vseq.sv:961) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop has 3 failures:
Test i2c_target_stress_all has 1 failures.
24.i2c_target_stress_all.60871676035274922782823188242664000640973537790134303724026744207050768209887
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1490819430 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 1490819430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_fifo_reset_tx has 2 failures.
41.i2c_target_fifo_reset_tx.87604329297418377629268383341968635068337833526693251274130601017738634060603
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest/run.log
UVM_ERROR @ 42794141 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 42794141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.i2c_target_fifo_reset_tx.55925260124135440148229258338294151708707050136696571947482630198046825750891
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_fifo_reset_tx/latest/run.log
UVM_ERROR @ 19984617 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 19984617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
1.i2c_target_stress_all_with_rand_reset.88914234394308503037406756994948426802849352032935031462690719582752448032663
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1179207467 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1179207467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stress_all_with_rand_reset.100795764304724302223720925156409153578953208477347456018577390673940271615294
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 437580169 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 437580169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 2 failures:
10.i2c_host_mode_toggle.85304505647374584912681306510613711794812514572576207377159429766383999620344
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 73180993 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
12.i2c_host_mode_toggle.73654907196065927299906056301598225412825831541487014319848812172667841460796
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 86504647 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
UVM_FATAL (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred! has 2 failures:
25.i2c_target_stress_all_with_rand_reset.79142419059032042398975529868724520757072776946821612261982985300205800637809
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1186883180 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
UVM_INFO @ 1186883180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.i2c_target_stress_all_with_rand_reset.29662391601200410689652562919798315165268415621365036253626182517847191917908
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1103589897 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
UVM_INFO @ 1103589897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
7.i2c_target_stress_all_with_rand_reset.33586313378314296783108298951176601167439499766680607272323079678238550712933
Line 325, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29362843282 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 234 [0xea])
UVM_INFO @ 29362843282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_monitor.sv:448) monitor [monitor] ack_stop detected has 1 failures:
9.i2c_target_hrst.42200756280149832066338405553550841506282282609840709245506613799365062359007
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_hrst/latest/run.log
UVM_ERROR @ 153261847 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 153261847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
9.i2c_same_csr_outstanding.80702963065791144761573059892119004890790603551388753736129910189178825662004
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 38087303 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 38087303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 1 failures:
20.i2c_target_stress_all_with_rand_reset.33652979651494708508806407186168744830723886052065119938140618787381300604733
Line 421, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 100349531488 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100349531488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---