c30684b3ca| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.987m | 9.840ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 54.832m | 100.000ms | 9 | 50 | 18.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.760s | 37.043us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.760s | 25.867us | 19 | 20 | 95.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.570s | 1.261ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.500s | 109.316us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.600s | 108.337us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.760s | 25.867us | 19 | 20 | 95.00 |
| i2c_csr_aliasing | 1.500s | 109.316us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 113 | 155 | 72.90 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.180s | 53.186us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.453m | 19.431ms | 41 | 50 | 82.00 |
| V2 | host_perf | i2c_host_perf | 15.767m | 25.847ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.740s | 15.808us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 9.492m | 52.723ms | 47 | 50 | 94.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 4.794m | 7.092ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.160s | 150.919us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 35.620s | 2.281ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 15.670s | 274.465us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.694m | 15.148ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 58.390s | 4.996ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 5.697m | 46.565ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 5.085m | 3.277ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 8.760s | 9.731ms | 50 | 50 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 13.010s | 17.289ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 31.116m | 50.015ms | 40 | 50 | 80.00 |
| V2 | target_perf | i2c_target_perf | 5.730s | 937.490us | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 35.295m | 100.000ms | 29 | 50 | 58.00 |
| i2c_target_intr_smoke | 8.740s | 5.763ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.249m | 10.097ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.694m | 10.113ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 48.794m | 64.641ms | 49 | 50 | 98.00 |
| i2c_target_stress_rd | 35.295m | 100.000ms | 29 | 50 | 58.00 | ||
| i2c_target_intr_stress_wr | 10.956m | 23.688ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 9.810s | 4.796ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 39.241m | 32.291ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.270s | 7.741ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.630s | 3.282ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.660s | 112.603us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.730s | 22.256us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.020s | 139.804us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.020s | 139.804us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.760s | 37.043us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.760s | 25.867us | 19 | 20 | 95.00 | ||
| i2c_csr_aliasing | 1.500s | 109.316us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.060s | 152.008us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.760s | 37.043us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.760s | 25.867us | 19 | 20 | 95.00 | ||
| i2c_csr_aliasing | 1.500s | 109.316us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.060s | 152.008us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1394 | 1442 | 96.67 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.210s | 632.705us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.540s | 877.834us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.210s | 632.705us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 19.713m | 36.217ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 17.657m | 100.298ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 1532 | 1722 | 88.97 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 5 | 71.43 |
| V2 | 31 | 31 | 25 | 80.65 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.47 | 98.70 | 96.00 | 100.00 | 92.17 | 97.21 | 100.00 | 91.18 |
UVM_ERROR (cip_base_vseq.sv:827) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 55 failures:
0.i2c_host_stress_all_with_rand_reset.23409656283409236875862685822349982381975822818658781375903568852043807285783
Line 4868, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27841236742 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 27841236742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.15437746912623132881497785701896707882769867229441369145177361873551947965464
Line 3012, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9889374125 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9889374125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 44 more failures.
0.i2c_target_stress_all_with_rand_reset.23808541052963901035894360184514887021058151912058282856913972028830706764864
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 115330673 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 115330673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.88667151040622146804924117702157413811783103402445048053369783477007104119787
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 656150172 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 656150172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 33 failures:
0.i2c_target_smoke.31718046606407591660090768254144890824452240635184715831175048010952698419150
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_smoke/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_smoke.24965820816661488400254335215093993255073452561971446125631876635036086215364
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_smoke/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
1.i2c_target_stress_rd.30083417662882248062493007272940378688984727299363178666709643396102968255186
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_rd/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_rd.67648314578360524292472302919801632036422455641572021109635750161596044292970
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_rd/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 33 failures:
Test i2c_target_smoke has 4 failures.
4.i2c_target_smoke.5957456020775350252188658356778907043305487253913290755232806270837144343667
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_smoke/latest/run.log
Job ID: smart:fbd6c2ce-f124-4353-be84-f6317d204ea6
12.i2c_target_smoke.25105741842077288263579602097550097745047137569399028523784802615760986689946
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_smoke/latest/run.log
Job ID: smart:2ec87715-8b0d-47e8-a0f8-b973065bb94a
... and 2 more failures.
Test i2c_target_stress_rd has 14 failures.
8.i2c_target_stress_rd.5395194440691625132810742635142923818443160188194974248135033435689854714624
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_rd/latest/run.log
Job ID: smart:6d119ff5-f70b-40f7-9ae6-e87b4ffc1a95
13.i2c_target_stress_rd.13524235678185155947992772244997829485839405449371298800894055637796593248296
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_rd/latest/run.log
Job ID: smart:2550e0c4-29fd-4d8a-b0d5-b8550da65b72
... and 12 more failures.
Test i2c_target_stress_all_with_rand_reset has 1 failures.
9.i2c_target_stress_all_with_rand_reset.15036463975915789592808756053582550976386765586839129076816370037440616933848
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b81b09f2-ba45-41ef-8511-088042af73a0
Test i2c_host_stress_all has 5 failures.
12.i2c_host_stress_all.75832182923079818747935331359771549361930005904695050702158607892236405431274
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
Job ID: smart:bb62f44a-0ffb-47de-a23b-53e1930aa04e
17.i2c_host_stress_all.33094635047185379719467780064758245109726499796561356906893104627151344276061
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log
Job ID: smart:b8450e1e-c28c-4426-8fd4-7933db8f103f
... and 3 more failures.
Test i2c_target_stretch has 4 failures.
14.i2c_target_stretch.22751980592716108856730792207738466953429708614085782106750785876675038897575
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stretch/latest/run.log
Job ID: smart:48c3047e-81a8-44fb-b986-ed8fe0c16bdf
20.i2c_target_stretch.107508287109618098416160516961875695085943770513263950657013689580459473119786
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stretch/latest/run.log
Job ID: smart:c2521272-2ec4-4542-9e90-7867c902f5c7
... and 2 more failures.
... and 2 more tests.
Job i2c-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 11 failures:
2.i2c_target_smoke.41105979574642991142706786558698919660119103967581918603833848092872388882916
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_smoke/latest/run.log
Job ID: smart:6e417cee-d188-485c-bbbd-8e1b282ccedf
5.i2c_target_smoke.84314910340400001708331808974671636298581903374898548556285110558908078651660
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_smoke/latest/run.log
Job ID: smart:361043a0-9da4-4f3f-9404-637568d200b5
... and 9 more failures.
UVM_FATAL (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred! has 10 failures:
1.i2c_target_stress_all.85704847923158201868943225720773290990817362190108423904919551947254272381212
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 80328725865 ps: (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 80328725865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.63049508208223974299882086292639715973900331228881348353560529234265937555292
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 55600875108 ps: (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 55600875108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 9 failures:
3.i2c_target_stress_all_with_rand_reset.105504508720144156779806478264746764803525343453337273541691673959561864187734
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 231066345 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x7a978a14) == 0x0
UVM_INFO @ 231066345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all_with_rand_reset.81698522919144994472415657942154515581946638781731617872893866103750708342071
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 541480602 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x1ade5414) == 0x0
UVM_INFO @ 541480602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred! has 8 failures:
7.i2c_target_stress_all_with_rand_reset.23582477794883506868532484912290522846125524016770739044435587299051727620760
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1078979276 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
UVM_INFO @ 1078979276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.28473858581106705982223389117417062221253523472968632354484327670245059198414
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1099126862 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
UVM_INFO @ 1099126862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 8 failures:
12.i2c_target_stress_all_with_rand_reset.47375528237228495274491317320852193882169232140131510717996950775560863337265
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3985656056 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 4 [0x4])
UVM_INFO @ 3985656056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stress_all_with_rand_reset.51462010670987360041495724615320273132100870431847418893836051521029224012331
Line 288, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3735694937 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 8 [0x8])
UVM_INFO @ 3735694937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:55) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 7 failures:
5.i2c_host_fifo_watermark.22783005240577625086018548731653352161323653882296498018824065336233638374387
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest/run.log
UVM_ERROR @ 329081225 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 329081225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_host_fifo_watermark.2354785503140299541991902397787826434895919052827716864910415720983411350873
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_fifo_watermark/latest/run.log
UVM_ERROR @ 186448428 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 186448428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
11.i2c_host_stress_all.112154044329704400807048843854785581742284769402389031063436282792367874807894
Line 4779, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 59911676768 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 59911676768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_host_stress_all.105711181417863737268095818530510873177361396203966924489955053326489325983300
Line 7705, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 16594072929 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 16594072929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 6 failures:
4.i2c_target_stress_all_with_rand_reset.81295395009707349855131232453847375789292119314653827971436806773324020406512
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2276665470 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (228 [0xe4] vs 240 [0xf0])
UVM_INFO @ 2276665470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stress_all_with_rand_reset.102650802826948529308299834238409950561659572668708807472118354279357805054896
Line 310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 98627214016 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (100 [0x64] vs 34 [0x22])
UVM_INFO @ 98627214016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 5 failures:
1.i2c_target_stress_all_with_rand_reset.23480107580885735722013343643383971732387770732820477768136092173047962994437
Line 318, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20006834858 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 20006834858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.74518805648154929074775777119453122499684551180877614496909351095345924833752
Line 346, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23033111555 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 23033111555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending 'scl_o' has 1 failures:
5.i2c_csr_rw.48244563080750873037081869842906014179225996202762167979788719584877895128650
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_csr_rw/latest/run.log
Offending 'scl_o'
UVM_ERROR @ 16297296 ps: (i2c_fsm.sv:1359) [ASSERT FAILED] SclOutputGlitch_A
UVM_INFO @ 16297296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
10.i2c_target_stress_all_with_rand_reset.85658145327272469383907739405553394649907909204973573103075931094340254506612
Line 372, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38513137297 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 144 [0x90])
UVM_INFO @ 38513137297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 1 failures:
13.i2c_target_stress_all_with_rand_reset.100809094586959221543010562444176928075726307991609645521784673537907808938669
Line 488, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 100298454266 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100298454266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_i' has 1 failures:
37.i2c_target_stress_all_with_rand_reset.18543319115800112962808639800063068150675801912188094658312170695185926422195
Line 347, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 15763218547 ps: (i2c_fsm.sv:1356) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 15763218547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
49.i2c_target_stress_all_with_rand_reset.109333824500607984405358450786478187458772871225816051446761411368529424264610
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 445306333 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 445306333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---