0cdf265eaa| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 3.195m | 2.756ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 49.691m | 100.000ms | 8 | 50 | 16.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.750s | 28.826us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.760s | 40.764us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.290s | 668.090us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.390s | 118.558us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.630s | 100.955us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.760s | 40.764us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.390s | 118.558us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 113 | 155 | 72.90 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.020s | 568.654us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 55.205m | 100.271ms | 25 | 50 | 50.00 |
| V2 | host_perf | i2c_host_perf | 41.778m | 50.823ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.680s | 20.129us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 10.146m | 6.560ms | 47 | 50 | 94.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.419m | 11.174ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.200s | 394.977us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 47.930s | 3.072ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 16.140s | 331.433us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.115m | 51.455ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 49.890s | 4.369ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 5.159m | 11.940ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 3.765m | 3.297ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 10.520s | 8.700ms | 50 | 50 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 4.810s | 2.287ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 38.779m | 94.166ms | 48 | 50 | 96.00 |
| V2 | target_perf | i2c_target_perf | 6.870s | 4.329ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 42.167m | 100.000ms | 21 | 50 | 42.00 |
| i2c_target_intr_smoke | 8.400s | 11.544ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.623m | 10.084ms | 49 | 50 | 98.00 |
| i2c_target_fifo_reset_tx | 1.453m | 10.065ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 54.154m | 60.370ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 42.167m | 100.000ms | 21 | 50 | 42.00 | ||
| i2c_target_intr_stress_wr | 18.138m | 26.427ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.960s | 2.355ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 43.840m | 34.950ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.450s | 3.359ms | 48 | 50 | 96.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.520s | 4.480ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.670s | 30.783us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 26.407us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.900s | 627.556us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.900s | 627.556us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.750s | 28.826us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.760s | 40.764us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.390s | 118.558us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.040s | 41.377us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.750s | 28.826us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.760s | 40.764us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.390s | 118.558us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.040s | 41.377us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 1371 | 1442 | 95.08 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.140s | 114.691us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.960s | 131.132us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.140s | 114.691us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 16.681m | 40.022ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 4.342m | 14.242ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 1509 | 1722 | 87.63 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 31 | 31 | 22 | 70.97 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.84 | 98.90 | 96.41 | 100.00 | 93.04 | 97.75 | 100.00 | 91.81 |
UVM_ERROR (cip_base_vseq.sv:815) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:
1.i2c_host_stress_all_with_rand_reset.12486521798838498524926901998964743838484309888270943770793882271909183669177
Line 1286, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 482797366 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 482797366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_stress_all_with_rand_reset.51375324302530021869832085861425828157740065472425257037363020354201458266535
Line 2385, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3139322818 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3139322818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 36 more failures.
5.i2c_target_stress_all_with_rand_reset.3923405026487123330571282120420958695794287979712832470702629422100857401145
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 431768036 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 431768036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.7829782208878103838412030403426073795602477561358833502239780526437378141773
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 234541504 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 234541504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 46 failures:
Test i2c_target_smoke has 28 failures.
0.i2c_target_smoke.66527605719417149842382571381053302860323772589174305814556818430534033034148
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_smoke/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_smoke.29252120105050387182019540882067497284263386648077772891205994467248866364729
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_smoke/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
Test i2c_target_stress_rd has 15 failures.
1.i2c_target_stress_rd.101659829635914027379927549012316979944375606686111495749272185394011006471556
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_rd/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_rd.17149048567495097980776823388858500132817842603866830590914738570144208979269
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_rd/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
Test i2c_target_bad_addr has 2 failures.
20.i2c_target_bad_addr.7019627630276602149855236449963188121022708015309603280694459538233507448547
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.i2c_target_bad_addr.50532020367971938469938314961916738809960251443352839972383044781835891548695
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_fifo_reset_acq has 1 failures.
40.i2c_target_fifo_reset_acq.44260724420107613582169134822976031346166321402957252178091588006690542984175
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_fifo_reset_acq/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 41 failures:
1.i2c_target_smoke.95913180983860968491866722606028503362671014974044414829809232957889222446099
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_smoke/latest/run.log
Job ID: smart:fbb2fd9d-f5cc-45c3-ab3a-4ee9d84df0df
17.i2c_target_smoke.15558568671085357607076164268375683019752589660245436046798703968788669308876
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_smoke/latest/run.log
Job ID: smart:6b833123-ab38-4b51-aff1-41dd54fa4dac
... and 6 more failures.
2.i2c_target_stress_rd.54736753941858642037261662450037695953708107966701724096228749266290200900121
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_rd/latest/run.log
Job ID: smart:39e419e2-0980-43ba-8c3b-dfc0b12479b3
3.i2c_target_stress_rd.77828607765244730996858163002593014925504902370119669792349601700003318965603
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_rd/latest/run.log
Job ID: smart:3f4b284b-eb96-4cc8-8f6c-63c9c3655a13
... and 12 more failures.
4.i2c_host_stress_all.71417457425136579890257507161260909270112078372151309890142045605564101533069
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
Job ID: smart:8dd641b9-2c87-4463-a164-b797611560e8
6.i2c_host_stress_all.41612076988745810729039912086348400342606160466522306347452927946663243960971
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
Job ID: smart:8e4bdd4c-c862-4992-8611-a801e390e16a
... and 5 more failures.
7.i2c_target_stretch.22873889001484659700301457567430067406235285509343928127438071455074937328693
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
Job ID: smart:c220c8a9-3792-4a64-bbb4-6f03e453e4d8
29.i2c_target_stretch.73242073073450708969096115450807838269795340141863404657363415500882605449944
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stretch/latest/run.log
Job ID: smart:2e839348-efc0-4d9b-828f-0e726d452ddb
... and 2 more failures.
9.i2c_host_stress_all_with_rand_reset.2914476965914612724136930414781490476377816560766105481491867446076382017933
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:5c8f4a02-bab6-4d51-8275-2fc1a49065cd
13.i2c_host_stress_all_with_rand_reset.77725344411969718536079476558384833371017305828625947153438989306719445556807
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:3d2050a8-ac5d-4714-b3c1-4be949afe722
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:461) [i2c_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRi2c_reg_block.intr_state has 25 failures:
0.i2c_host_stress_all_with_rand_reset.97336322188513225921255683033522294646845185715479652960181438901599135878511
Line 454, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6805201362 ps: (cip_base_vseq.sv:461) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed exp_val == act_val (2566 [0xa06] vs 2567 [0xa07]) when reading the intr CSRi2c_reg_block.intr_state
UVM_INFO @ 6805201362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_host_stress_all_with_rand_reset.106094837844988426359467536775007341011402820043146443276395390340703312743607
Line 456, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25006665986 ps: (cip_base_vseq.sv:461) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed exp_val == act_val (22124 [0x566c] vs 24173 [0x5e6d]) when reading the intr CSRi2c_reg_block.intr_state
UVM_INFO @ 25006665986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
2.i2c_host_stress_all.18182983136054761107466194246925611406805872616578935338447906288558093838674
Line 9736, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 17570004472 ps: (cip_base_vseq.sv:461) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed exp_val == act_val (10876 [0x2a7c] vs 10877 [0x2a7d]) when reading the intr CSRi2c_reg_block.intr_state
UVM_INFO @ 17570004472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_stress_all.10122048752044058238730831037638785285587463404903306787452289139928145481916
Line 1503, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 22095638064 ps: (cip_base_vseq.sv:461) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed exp_val == act_val (28947 [0x7113] vs 30995 [0x7913]) when reading the intr CSRi2c_reg_block.intr_state
UVM_INFO @ 22095638064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 9 failures:
10.i2c_target_stress_all_with_rand_reset.108098972127889250971947614029056928680422307331903992240374246280541442183193
Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 454235858 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 454235858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_stress_all_with_rand_reset.96528549791397944114765129898071178737649618271223368843672532789481221708043
Line 285, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7592858299 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 7592858299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 7 failures:
2.i2c_target_stress_all_with_rand_reset.30694387711802831584820312479766256978425765361718045828845355431851120276217
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8520726934 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 9 [0x9])
UVM_INFO @ 8520726934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.28246759828819193236603581063080431790491198638745713800391468748381312970693
Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1379282346 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 2 [0x2])
UVM_INFO @ 1379282346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 6 failures:
3.i2c_target_smoke.56149801088477682230460265327613418823158541310282799760505793080719263230931
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_smoke/latest/run.log
Job ID: smart:9de8939f-4c86-4ce6-9e73-2b975e2239ce
10.i2c_target_smoke.73829003924025545585421324729405564083596029135274406478393070360928252480479
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_smoke/latest/run.log
Job ID: smart:deaf11dc-eeca-458b-b78b-13034ffcbdce
... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:741) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 6 failures:
4.i2c_target_stress_all_with_rand_reset.15713658352640958378718037430358174399252888922592166522686774956615870185377
Line 310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14241898105 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 14241898105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_stress_all_with_rand_reset.103512282575704060858251502109987880300977164847646024405758081500165253534760
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1982368185 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1982368185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred! has 5 failures:
0.i2c_target_stress_all_with_rand_reset.46549424061579847087598624275336178306609050126312002739727631807523380936523
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1179985630 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
UVM_INFO @ 1179985630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.62418417343949796166866569083616962849520062762880905762480423640763974792828
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1247185291 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
UVM_INFO @ 1247185291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending 'scl_i' has 5 failures:
1.i2c_target_stress_all_with_rand_reset.1421039219352977742030841981652202971517753463341510467651914486816201556992
Line 329, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 79686483728 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 79686483728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_target_stress_all_with_rand_reset.98809492647480885019438073646112768394503447278688382367658845975753793331192
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 3086969118 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 3086969118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:55) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 5 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
2.i2c_host_stress_all_with_rand_reset.56059516181593422728038924604624150466847596363363902779172728275536755083772
Line 3275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7046481437 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 7046481437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_fifo_watermark has 3 failures.
16.i2c_host_fifo_watermark.36020204295662371107336485017557232008612357540815137651483437964083651741835
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_fifo_watermark/latest/run.log
UVM_ERROR @ 205703275 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 205703275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.i2c_host_fifo_watermark.77046274788801649727491463064135308178479088643816754775115616093052980477256
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_fifo_watermark/latest/run.log
UVM_ERROR @ 566846878 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 566846878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test i2c_host_stress_all has 1 failures.
17.i2c_host_stress_all.68756940173710138456865295470825972566315126199919484877934864803573835093882
Line 2053, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 11092086585 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 11092086585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 5 failures:
13.i2c_target_stress_all_with_rand_reset.575675510803424302830678668729159829826627441976980185643432936406399440749
Line 340, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 36307123184 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xd69c9394) == 0x0
UVM_INFO @ 36307123184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stress_all_with_rand_reset.83566384348051335121612980666467607193846409774676812938546320928678477954636
Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 17713007327 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x79a3d94) == 0x0
UVM_INFO @ 17713007327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:491) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
6.i2c_same_csr_outstanding.4148820202548826065809158801896826100106347323380389261434257279585812102685
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 26028534 ps: (cip_base_vseq.sv:491) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 26028534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_same_csr_outstanding.90007556748285941239304809537762843884411526130138436795264167122145349111986
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 74963423 ps: (cip_base_vseq.sv:491) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 74963423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 2 failures:
17.i2c_target_stress_all_with_rand_reset.85754379664387026062593965015618940039856711535055524019458058685803054804204
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 893077977 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 47 [0x2f])
UVM_INFO @ 893077977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.i2c_target_stress_all_with_rand_reset.26207357264172745027786473967470484706155470019784019798395642069920437144477
Line 390, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16595984800 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 244 [0xf4])
UVM_INFO @ 16595984800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
20.i2c_target_stress_all_with_rand_reset.27445065571376606184806562889816675342254072107623675230318376044387868771043
Line 382, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 48644209668 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (44 [0x2c] vs 252 [0xfc])
UVM_INFO @ 48644209668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.i2c_target_stress_all_with_rand_reset.104772234301801093057779246130171007504759842991493212179474244136010652087308
Line 291, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25072535647 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (4 [0x4] vs 203 [0xcb])
UVM_INFO @ 25072535647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---