bc285b7382| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.277m | 10.537ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 41.032m | 100.000ms | 9 | 50 | 18.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.690s | 24.866us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.730s | 20.775us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.490s | 954.227us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.460s | 137.685us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.230s | 94.822us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.730s | 20.775us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.460s | 137.685us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 114 | 155 | 73.55 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.130s | 83.809us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 55.917m | 15.524ms | 40 | 50 | 80.00 |
| V2 | host_perf | i2c_host_perf | 19.995m | 23.852ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.690s | 16.744us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 8.482m | 14.819ms | 44 | 50 | 88.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.944m | 7.688ms | 49 | 50 | 98.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.180s | 291.374us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 39.130s | 695.145us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 14.440s | 254.748us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.808m | 3.430ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 50.550s | 18.849ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.539m | 5.140ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 8.530s | 6.604ms | 47 | 50 | 94.00 |
| V2 | target_glitch | i2c_target_glitch | 12.850s | 10.930ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 37.675m | 63.381ms | 21 | 50 | 42.00 |
| V2 | target_perf | i2c_target_perf | 5.480s | 894.694us | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 26.174m | 100.000ms | 28 | 50 | 56.00 |
| i2c_target_intr_smoke | 9.070s | 9.727ms | 42 | 50 | 84.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.550m | 10.058ms | 42 | 50 | 84.00 |
| i2c_target_fifo_reset_tx | 1.708m | 10.059ms | 46 | 50 | 92.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 17.818m | 69.624ms | 41 | 50 | 82.00 |
| i2c_target_stress_rd | 26.174m | 100.000ms | 28 | 50 | 56.00 | ||
| i2c_target_intr_stress_wr | 11.047m | 24.336ms | 43 | 50 | 86.00 | ||
| V2 | target_timeout | i2c_target_timeout | 9.250s | 10.059ms | 42 | 50 | 84.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 59.624m | 39.544ms | 33 | 50 | 66.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.180s | 1.643ms | 41 | 50 | 82.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.450s | 12.506ms | 41 | 50 | 82.00 |
| V2 | alert_test | i2c_alert_test | 0.640s | 28.363us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.700s | 41.682us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.750s | 160.017us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.750s | 160.017us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.690s | 24.866us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.730s | 20.775us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.460s | 137.685us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.100s | 58.652us | 15 | 20 | 75.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.690s | 24.866us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.730s | 20.775us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.460s | 137.685us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.100s | 58.652us | 15 | 20 | 75.00 | ||
| V2 | TOTAL | 1237 | 1392 | 88.86 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.980s | 195.645us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.940s | 138.157us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.980s | 195.645us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.809m | 20.078ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 13.553m | 100.479ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 1376 | 1672 | 82.30 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 31 | 30 | 14 | 45.16 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.94 | 98.90 | 96.41 | 100.00 | 93.91 | 97.64 | 100.00 | 91.70 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 75 failures:
Test i2c_target_stress_all has 15 failures.
0.i2c_target_stress_all.91655505515792667872616819281211184808362461002564289188911731362048894736390
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 162943660 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 162943660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.2737410766931261079580882150982312310611259016179881570072626771227377920458
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 46244513 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 46244513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
Test i2c_target_bad_addr has 2 failures.
0.i2c_target_bad_addr.24042390204606073093786687389770269929369339275440202464467680460972247718515
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_bad_addr/latest/run.log
UVM_ERROR @ 233303489 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 233303489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.i2c_target_bad_addr.68621086412994279779026393403880698693636739381021172439701262532489933276113
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_bad_addr/latest/run.log
UVM_ERROR @ 71273563 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 71273563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_wr has 9 failures.
1.i2c_target_stress_wr.32185910825292840938042281501950373978815741738555089668106972037669931549444
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_wr/latest/run.log
UVM_ERROR @ 61915837 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 61915837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_wr.104476256501266716677964960987578860734500568035767859080516714651329759909551
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_wr/latest/run.log
UVM_ERROR @ 39633142 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 39633142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test i2c_target_intr_stress_wr has 7 failures.
1.i2c_target_intr_stress_wr.2325097050628395454772736711390145960962895586744980599291131018825556278504
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest/run.log
UVM_ERROR @ 550187640 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 550187640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.i2c_target_intr_stress_wr.102446305659326028357309331782606482358913484442627524172102566878287608408827
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_intr_stress_wr/latest/run.log
UVM_ERROR @ 289462913 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 289462913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test i2c_target_fifo_reset_acq has 5 failures.
2.i2c_target_fifo_reset_acq.106003153258648761396342054014162838732366347570580917426896523428695501112431
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_fifo_reset_acq/latest/run.log
UVM_ERROR @ 25098176 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 25098176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_fifo_reset_acq.112558720690740786487129851139088091780596503729390405558146596248576819879784
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_fifo_reset_acq/latest/run.log
UVM_ERROR @ 40794091 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 40794091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
... and 7 more tests.
UVM_ERROR (cip_base_vseq.sv:827) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 49 failures:
1.i2c_host_stress_all_with_rand_reset.52301865711069750423662117070759340819063349907255115489211715348088446327678
Line 7670, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9240523268 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9240523268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.38889829242720569620643348076623224799276663927106301232554684770820086469287
Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 794757319 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 794757319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 44 more failures.
1.i2c_target_stress_all_with_rand_reset.63783546694373899165745681724931833037895683534135669115192942566185568869607
Line 305, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5147639894 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5147639894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stress_all_with_rand_reset.41556634478117127144240276319032521910160248895783699772118382166197637546456
Line 332, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10038023437 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10038023437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:773) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 44 failures:
2.i2c_target_stress_rd.34503083410660858849758098238762670345377091135304065051864935335165815032980
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_rd/latest/run.log
UVM_ERROR @ 17287870 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 17287870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stress_rd.111514317496619434338813274333996022047511325603212515747276014643790943759411
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_rd/latest/run.log
UVM_ERROR @ 139818122 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 139818122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
2.i2c_target_stress_all.13772923683194556022794684790216034485949036162798812354136912440141158063658
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 14741808 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 14741808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all.103189520909922934094853338102982546491287880990418860413483812053664812705456
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 7538280401 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7538280401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
3.i2c_target_bad_addr.15237991065447646560729144246388179976852051732898016535592150382797249605294
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_bad_addr/latest/run.log
UVM_ERROR @ 5511548 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5511548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_bad_addr.3455705715395848287132714229168966211032860342008427164049408451858532507751
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_bad_addr/latest/run.log
UVM_ERROR @ 52222077 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 52222077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
7.i2c_target_smoke.74036532336779262761089568526536795951166859282186233058788140785674936967559
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_smoke/latest/run.log
UVM_ERROR @ 82202505 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 82202505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_smoke.34569755828758357483911293461113650820340230502416811952876172155097233173321
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_smoke/latest/run.log
UVM_ERROR @ 28242735 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 28242735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
11.i2c_target_intr_smoke.97456402685498862494898920913245026335419372407430838017344622613059801142773
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_intr_smoke/latest/run.log
UVM_ERROR @ 321788743 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 321788743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_intr_smoke.76427538500176396428116328923560409571372350661244812777364107486293872330190
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_intr_smoke/latest/run.log
UVM_ERROR @ 18345882 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 18345882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 36 failures:
0.i2c_host_stress_all_with_rand_reset.92707357736814475163781726835243479603381012297482801329529222255495318013969
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:aea4128c-8886-43d9-a8ed-0e75f6dbf189
16.i2c_host_stress_all_with_rand_reset.114184975612077067022315957193737244434854834780864868068856651163141716900234
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:2f336979-416b-4273-834c-60dc28fabfab
... and 2 more failures.
1.i2c_host_stress_all.45926514995697562471576534121944358095363412840661285638670678390077514454715
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:8e38ba9d-7ee3-42d6-bbad-7042b2a1fb59
2.i2c_host_stress_all.69552497631653628361843404323899672277588027106870704692166648913006294519191
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:8eebdf02-66a5-486c-a52b-1a8abd22ec3a
... and 5 more failures.
1.i2c_target_smoke.47000452554244490117569338366748175341972773769347722258727984456507151861348
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_smoke/latest/run.log
Job ID: smart:24ba703f-a5d5-4799-b783-dffeb30ce5ee
17.i2c_target_smoke.96957207075245818641920882891286861957106820563432218679365680800646937006259
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_smoke/latest/run.log
Job ID: smart:40a286b6-cbac-4ea4-ade0-9278deb2d2e0
... and 2 more failures.
2.i2c_target_stretch.61466527257106251380876440490853092767848406444304954704932339048932569778903
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
Job ID: smart:506e02c6-ee67-4666-9e02-63c109affaa3
5.i2c_target_stretch.96405924484044382329996993847825802580220893336186167080104892489150102907744
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
Job ID: smart:c4ab9423-069f-473d-afa9-5d0cd95af4d8
... and 7 more failures.
3.i2c_target_stress_rd.24468022545373595805474029160533673362930686032295023094439227730260069868401
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_rd/latest/run.log
Job ID: smart:3deae4b1-1a0d-4b55-9d93-ee32e8a2c982
12.i2c_target_stress_rd.22846160434826490768523813346918933466739174153293334667542446609138932843339
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_rd/latest/run.log
Job ID: smart:b8b83e46-b7b6-4de5-81d7-ed5eda4b69f9
... and 9 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 25 failures:
4.i2c_target_smoke.68095860163378902784776366641798736371512092560474531660677560766936485663130
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_smoke/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_smoke.69418046572104997390558471596213294360732217650685243553449772594087528612628
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_smoke/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
6.i2c_target_stress_rd.70943492769178779174718805786988167812643543523008932878533512139385029160185
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_rd/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stress_rd.20469264758482435261200749482082208237472015848281835966000125698488529578157
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_rd/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 13 failures:
2.i2c_target_stress_all_with_rand_reset.82768957517215572707168020116048096052077116792352336163244319379506515358612
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 191536703 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 24 [0x18])
UVM_INFO @ 191536703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.112525600461649380671003434513236811960315068816819264418759245811541468906522
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 276835506 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 9 [0x9])
UVM_INFO @ 276835506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:55) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 9 failures:
5.i2c_host_fifo_watermark.100184308239063265998322087268692113153113295325020074085045930161373967524872
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest/run.log
UVM_ERROR @ 541707473 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 541707473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_host_fifo_watermark.43476214601970162732832828092928659017475740166539806572317102949540305389708
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_fifo_watermark/latest/run.log
UVM_ERROR @ 267032104 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 267032104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
27.i2c_host_stress_all.68325004941624871083913839515498988642263050650135290498155834429371897729567
Line 3987, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 18849110949 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 18849110949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.i2c_host_stress_all.52806591526616364405231380925142557590331510714227492748945192085844814350889
Line 3908, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 60946491370 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 60946491370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 8 failures:
2.i2c_target_smoke.83539529779169402027538063812154359297381445916333255902190924752020171461300
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_smoke/latest/run.log
Job ID: smart:cfd6eda7-b371-47e9-8d9f-e4f3ef40fa76
3.i2c_target_smoke.12015149283633395541354650363748034854916005409057595353032612612134503475869
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_smoke/latest/run.log
Job ID: smart:48097192-7201-412f-a3ae-17979d0d68ff
... and 6 more failures.
UVM_FATAL (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred! has 7 failures:
6.i2c_target_stress_all.78410331905444340088702555143469882686746239773691445228993139831918336851957
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 31363771372 ps: (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 31363771372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stress_all.67531477048290134564112422243148338708232010309375812868496519940096640205886
Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 43526542873 ps: (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 43526542873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred! has 6 failures:
0.i2c_target_stress_all_with_rand_reset.53262034179907767687488829811240920204496128265239039072487196411455223273884
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1395193168 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
UVM_INFO @ 1395193168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.84030491746317986403229078262935695360931831634372209711683988477108312895775
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1532297506 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
UVM_INFO @ 1532297506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_base_vseq.sv:961) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop has 5 failures:
Test i2c_target_intr_smoke has 1 failures.
23.i2c_target_intr_smoke.45361097874030169542268074819094209202483052360816748565689790870556686157770
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_intr_smoke/latest/run.log
UVM_ERROR @ 27859736 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 27859736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_fifo_reset_acq has 3 failures.
25.i2c_target_fifo_reset_acq.108491436727566333337517133845885350831393804605272709826223114284895299147473
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_fifo_reset_acq/latest/run.log
UVM_ERROR @ 165719966 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 165719966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.i2c_target_fifo_reset_acq.14255245556352360440653456664795861389171718064319026261993105606599924043597
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_fifo_reset_acq/latest/run.log
UVM_ERROR @ 22199075 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 22199075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test i2c_target_stress_all has 1 failures.
38.i2c_target_stress_all.99034545463492776377711391360329071275400867245049863438459269644867906617019
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 33381844599 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 33381844599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_i' has 4 failures:
0.i2c_same_csr_outstanding.10026536956436019190255966227855243737082704934420767723728002002225140525009
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 26501306 ps: (i2c_fsm.sv:1356) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 26501306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_same_csr_outstanding.51085689955389141474767316202222041302877555214196939352909098000201238809472
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 22417044 ps: (i2c_fsm.sv:1356) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 22417044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
24.i2c_target_stress_all_with_rand_reset.10092008867974584771505277527949733567590305185120040863261660329234333719823
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 806850424 ps: (i2c_fsm.sv:1356) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 806850424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 4 failures:
6.i2c_target_stress_all_with_rand_reset.69759899053413676645629865027676155139373242319687485297161608515711324241384
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1836792496 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1836792496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.i2c_target_stress_all_with_rand_reset.75993236008746062066447261445175491201162287071310037797994329673190310834737
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 190411100 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 190411100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
7.i2c_target_stress_all_with_rand_reset.97355350558381891140988068874646603861179810750890078510324176177624514399107
Line 308, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 59416959149 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x6404e814) == 0x0
UVM_INFO @ 59416959149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all_with_rand_reset.84979450447369475488148977112281766895691040742360483576444184493444477615571
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2222979054 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xeebc4a14) == 0x0
UVM_INFO @ 2222979054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
11.i2c_target_stress_all_with_rand_reset.73421830062209605473529001584735920069424871093317752978033968516825821714486
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14535183118 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (46 [0x2e] vs 118 [0x76])
UVM_INFO @ 14535183118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_target_stress_all_with_rand_reset.53830492274255417056553448602270602688995845979124026038816890984183200729094
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 77500831 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (215 [0xd7] vs 143 [0x8f])
UVM_INFO @ 77500831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: Submit error: error submitting to edafarm: no job spec returned has 2 failures:
Test i2c_target_bad_addr has 1 failures.
26.i2c_target_bad_addr.115740208702516267718730664559835878391962526364290521302891986838427316902656
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_bad_addr/latest/run.log
Job ID: smart:bceb2658-5421-4b13-ad89-321fff647ac9
Test i2c_host_fifo_overflow has 1 failures.
27.i2c_host_fifo_overflow.102862489225239182548047336090145801411171917352223636629657374291008434540737
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_fifo_overflow/latest/run.log
Job ID: smart:68e83c02-fc23-47b9-bb5e-b243c5769742
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
6.i2c_same_csr_outstanding.95815932343849879692247364216989963649030587684864861375806692695733945134403
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 202031996 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 202031996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
10.i2c_target_stress_all_with_rand_reset.112162387695538307129671647353254703937789098718997600691809277125867375088709
Line 359, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9800567987 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 58 [0x3a])
UVM_INFO @ 9800567987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!((host_enable_i && (scl_d != scl_q)) && (sda_d != sda_q)))' has 1 failures:
18.i2c_same_csr_outstanding.86523112851661744762588125168117187101837451968858703213669131057524634110990
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest/run.log
Offending '(!((host_enable_i && (scl_d != scl_q)) && (sda_d != sda_q)))'
UVM_ERROR @ 109342826 ps: (i2c_fsm.sv:1368) [ASSERT FAILED] SclSdaChangeNotSimultaneous_A
UVM_INFO @ 109342826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 1 failures:
33.i2c_target_stress_all_with_rand_reset.115061939396024267992725431315260241272725860352841084555734893510757564251128
Line 407, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 100479425332 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100479425332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---