I2C Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	4.009m	4.132ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	43.974m	100.000ms	8	50	16.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.720s	44.880us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.770s	51.750us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.100s	481.560us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.480s	74.454us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.510s	32.500us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.770s	51.750us	20	20	100.00
		i2c_csr_aliasing	1.480s	74.454us	5	5	100.00
V1		TOTAL			113	155	72.90
V2	host_error_intr	i2c_host_error_intr	2.130s	47.951us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	52.981m	14.774ms	42	50	84.00
V2	host_perf	i2c_host_perf	17.628m	28.095ms	50	50	100.00
V2	host_override	i2c_host_override	0.710s	17.366us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	11.798m	13.570ms	44	50	88.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	4.413m	11.970ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.140s	125.525us	50	50	100.00
		i2c_host_fifo_fmt_empty	36.100s	2.520ms	50	50	100.00
		i2c_host_fifo_reset_rx	17.870s	1.142ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	4.787m	13.791ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	56.670s	2.530ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample	4.428m	12.085ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.325m	2.565ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	9.600s	8.596ms	50	50	100.00
V2	target_glitch	i2c_target_glitch	13.260s	4.844ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	34.898m	61.918ms	39	50	78.00
V2	target_perf	i2c_target_perf	5.870s	3.907ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	32.938m	100.000ms	24	50	48.00
		i2c_target_intr_smoke	8.620s	8.253ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.575m	10.054ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.656m	10.076ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	36.453m	64.322ms	50	50	100.00
		i2c_target_stress_rd	32.938m	100.000ms	24	50	48.00
		i2c_target_intr_stress_wr	11.846m	26.580ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.440s	24.340ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	56.199m	39.598ms	42	50	84.00
V2	bad_address	i2c_target_bad_addr	7.010s	1.839ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.650s	3.008ms	50	50	100.00
V2	alert_test	i2c_alert_test	0.640s	17.613us	50	50	100.00
V2	intr_test	i2c_intr_test	0.740s	26.691us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.750s	57.545us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.750s	57.545us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.720s	44.880us	5	5	100.00
		i2c_csr_rw	0.770s	51.750us	20	20	100.00
		i2c_csr_aliasing	1.480s	74.454us	5	5	100.00
		i2c_same_csr_outstanding	1.080s	98.795us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.720s	44.880us	5	5	100.00
		i2c_csr_rw	0.770s	51.750us	20	20	100.00
		i2c_csr_aliasing	1.480s	74.454us	5	5	100.00
		i2c_same_csr_outstanding	1.080s	98.795us	19	20	95.00
V2		TOTAL			1382	1442	95.84
V2S	tl_intg_err	i2c_tl_intg_err	2.170s	1.103ms	20	20	100.00
		i2c_sec_cm	0.960s	928.202us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.170s	1.103ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.774m	16.623ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.352m	68.591ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
		TOTAL			1520	1722	88.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	31	31	25	80.65
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.55	98.75	96.21	100.00	92.17	97.32	100.00	91.39

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 52 failures:

Test i2c_host_stress_all_with_rand_reset has 45 failures.

0.i2c_host_stress_all_with_rand_reset.21545262634435943891914831534415071199599893417828919744494804603910944546288
Line 2918, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4981326736 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4981326736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.37979993456233954221159679043740115974779210800996958688210615358596813731648
Line 4497, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 42351176499 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 42351176499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 43 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

0.i2c_target_stress_all_with_rand_reset.64663217266981738420765776661931516029330042882030326078975142735676968852039
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 108268386 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 108268386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.55177679492985666131356049489077337797464441470768993575858392473774080679093
Line 370, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16560661792 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16560661792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 43 failures:
- Test i2c_host_stress_all has 6 failures.
  - 0.i2c_host_stress_all.80606960557645499907331906697204849816331372381444821754646879683334352412035
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:3174618e-f0e1-4395-9977-28bf7b1bca67
```
  - 2.i2c_host_stress_all.108601339261059485622799232961108413716230633983915523662472672926114033071634
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:5bfbe6d0-e0f3-43db-bcb6-23277fbeecf3
```
  - ... and 4 more failures.
- Test i2c_target_smoke has 8 failures.
  - 0.i2c_target_smoke.80473862477727144559304471580718840299161384383123051608031238784553752931714
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_smoke/latest/run.log
```
  Job ID: smart:0f151eb2-d201-453a-9ff0-65fae46d8fae
```
  - 3.i2c_target_smoke.65823795181635193186812542794904321835196889647724020660833725249590004138491
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_smoke/latest/run.log
```
  Job ID: smart:c7f5c988-dbb2-4527-9b79-922a8525c2f9
```
  - ... and 6 more failures.
- Test i2c_target_stress_rd has 17 failures.
  - 2.i2c_target_stress_rd.44927670901271069324875013698877715116487287954968179013032356936462489914227
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_rd/latest/run.log
```
  Job ID: smart:bf42caf9-cb67-4624-8744-1b58d51b87a4
```
  - 11.i2c_target_stress_rd.100965873096763709675643267817988094031116067262720825586258081908310975763252
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_rd/latest/run.log
```
  Job ID: smart:83c77eaf-887a-4c61-abd8-aca5bb810703
```
  - ... and 15 more failures.
- Test i2c_host_stress_all_with_rand_reset has 4 failures.
  - 6.i2c_host_stress_all_with_rand_reset.1239621875056905198856795325368501433246113692074414724193410039314894480266
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:642d6886-db71-43c5-a84d-2cc9726b92eb
```
  - 17.i2c_host_stress_all_with_rand_reset.35381317917421142807048829092483105059168502380311376714884465150606864426246
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ccc4d0be-c9f9-479e-a952-233abd8379de
```
  - ... and 2 more failures.
- Test i2c_target_stretch has 8 failures.
  - 9.i2c_target_stretch.1722292038969137309897678053346155071819488330178660119750204402234388381830
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stretch/latest/run.log
```
  Job ID: smart:c8fb7cf9-afd8-4322-98ef-8c8a1002c881
```
  - 22.i2c_target_stretch.57188808907835571667973851554287541863815202340808086679656845781746409290356
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stretch/latest/run.log
```
  Job ID: smart:62dd3892-beea-4e8b-a625-9efdbac3c467
```
  - ... and 6 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 37 failures:

Test i2c_target_smoke has 28 failures.

1.i2c_target_smoke.70008124381674048272010993974235136696527770046288271266307713687770078983563
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_smoke/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_smoke.96726728364674619439616914182453644645078383243318635260219478706548471136902
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_smoke/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 26 more failures.

Test i2c_target_stress_rd has 9 failures.

1.i2c_target_stress_rd.36527635681602817938315474157371315674645766387776655568326579524173474729278
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_rd/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_rd.89629727103027210690971828612771205229500263090808680954828026544210384354536
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_rd/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 13 failures:
- Test i2c_target_stress_all_with_rand_reset has 13 failures.
  - 4.i2c_target_stress_all_with_rand_reset.36873184671434885920513918320385726414269726217336384508496390145558638776018
    Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1736242095 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 1736242095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.i2c_target_stress_all_with_rand_reset.47506605799887069711945114282088658320144195465862777392096668624056226143157
    Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1649054498 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 5 [0x5])
  UVM_INFO @ 1649054498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred! has 11 failures:
- Test i2c_target_stress_all has 11 failures.
  - 0.i2c_target_stress_all.2987788025481770195997226133393095244703632201022275746606659525493010411070
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 60822211076 ps: (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 60822211076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.i2c_target_stress_all.24136703708372884824598478188315397167018169867925676987829177807128316275359
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 28526708743 ps: (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 28526708743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:55) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 9 failures:

Test i2c_host_fifo_watermark has 6 failures.

3.i2c_host_fifo_watermark.45837068749061649766476436728214615284781810556486519746922991677403001645177
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_fifo_watermark/latest/run.log

  UVM_ERROR @ 159009153 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 159009153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.i2c_host_fifo_watermark.23084649828174124845876970857563504645625096191964624297651775603141372433447
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_fifo_watermark/latest/run.log

  UVM_ERROR @ 166047180 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 166047180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test i2c_host_stress_all has 2 failures.

4.i2c_host_stress_all.2068780955313252620230218250162302029194557205983750588069174172248961129742
Line 1644, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 21486709657 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 21486709657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.i2c_host_stress_all.79797245357919558593904263968354388857991002823371658153729568340403440286277
Line 1985, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 12474661665 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 12474661665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_stress_all_with_rand_reset has 1 failures.

39.i2c_host_stress_all_with_rand_reset.42114823683711481385925357236691015057508190704759337727024217915230071296422
Line 517, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 532089771 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 532089771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 9 failures:
- Test i2c_target_stress_all_with_rand_reset has 9 failures.
  - 7.i2c_target_stress_all_with_rand_reset.73839393374237364078367371930662490459992305717881298885396374818368312704912
    Line 308, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14166818706 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 14166818706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.i2c_target_stress_all_with_rand_reset.73843802349761273414855591977095772620803749589851389490058941580822309229425
    Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  55715884 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  55715884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 8 failures:
- Test i2c_target_stress_all_with_rand_reset has 8 failures.
  - 2.i2c_target_stress_all_with_rand_reset.30695760319426645206307783745601641260254421791118524126448221412485299670653
    Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 885983399 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x5042bc94) == 0x0
  UVM_INFO @ 885983399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.i2c_target_stress_all_with_rand_reset.115158703053004921447532765936610948339857587429852749218625143854706837045847
    Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 25797803922 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x96bf5914) == 0x0
  UVM_INFO @ 25797803922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred! has 6 failures:
- Test i2c_target_stress_all_with_rand_reset has 6 failures.
  - 3.i2c_target_stress_all_with_rand_reset.43976073764355356497028956643211588522783309223685743509241701162565421015525
    Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1542659448 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
  UVM_INFO @ 1542659448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_stress_all_with_rand_reset.98302880160419247966170001217904896092926047663006127962739481909415188503449
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1280913276 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
  UVM_INFO @ 1280913276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 6 failures:
- Test i2c_target_smoke has 6 failures.
  - 16.i2c_target_smoke.20133867608257590336015657605733521780943257609364348214105091104342418551225
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_smoke/latest/run.log
```
  Job ID: smart:10f0771d-a942-45b3-b10d-a0a3ce5411df
```
  - 17.i2c_target_smoke.36575724870334669814077247053670703725951908833253976986128578359665649230637
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_smoke/latest/run.log
```
  Job ID: smart:ac345b59-e6a4-4af8-b891-2496219e87bd
```
  - ... and 4 more failures.
Offending 'scl_i' has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 1.i2c_target_stress_all_with_rand_reset.38510416708181380992914465134133603253517474341604508616922489218302611467444
    Line 435, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending 'scl_i'
  UVM_ERROR @ 9901321954 ps: (i2c_fsm.sv:1356) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 9901321954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 17.i2c_target_stress_all_with_rand_reset.94988386870460132242377415048572089412683645859705387080884085073650129382072
    Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending 'scl_i'
  UVM_ERROR @ 604995755 ps: (i2c_fsm.sv:1356) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 604995755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_same_csr_outstanding has 1 failures.
  - 8.i2c_same_csr_outstanding.111146178970712446343935920703328562293804499275006252381122290843177798740787
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest/run.log
```
      Offending 'scl_i'
  UVM_ERROR @   2147241 ps: (i2c_fsm.sv:1356) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @   2147241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 30.i2c_target_stress_all_with_rand_reset.37918643423072826124397305672219039803168519764480374659346780479082087886148
    Line 362, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9594956568 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (155 [0x9b] vs 82 [0x52])
  UVM_INFO @ 9594956568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.i2c_target_stress_all_with_rand_reset.8792928400450419528826602166625681797065512871937539499075603294467815293109
    Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 354585302 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (76 [0x4c] vs 103 [0x67])
  UVM_INFO @ 354585302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 33.i2c_target_stress_all_with_rand_reset.73790734776948324157789499734581813663221350785533469844549490577916694468189
    Line 371, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63629218730 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 177 [0xb1])
  UVM_INFO @ 63629218730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.i2c_target_stress_all_with_rand_reset.90594260193038743416215086296329144101280721619319882913002834990333051129774
    Line 343, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20339288341 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (192 [0xc0] vs 67 [0x43])
  UVM_INFO @ 20339288341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```