f7fc348358| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.746m | 9.655ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 41.907m | 100.000ms | 10 | 50 | 20.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.770s | 84.163us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.730s | 23.176us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.040s | 356.056us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.750s | 311.578us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.540s | 65.533us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.730s | 23.176us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.750s | 311.578us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 115 | 155 | 74.19 | |||
| V2 | host_error_intr | i2c_host_error_intr | 1.980s | 360.425us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 50.869m | 11.947ms | 38 | 50 | 76.00 |
| V2 | host_perf | i2c_host_perf | 51.112m | 97.835ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.710s | 60.877us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 8.168m | 11.509ms | 43 | 50 | 86.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.774m | 11.182ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.250s | 616.489us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 36.190s | 2.475ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 16.650s | 296.046us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.078m | 3.079ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 48.910s | 4.723ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.880m | 2.282ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 8.780s | 3.863ms | 40 | 50 | 80.00 |
| V2 | target_glitch | i2c_target_glitch | 5.020s | 905.482us | 0 | 2 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 3.468m | 26.433ms | 11 | 50 | 22.00 |
| V2 | target_perf | i2c_target_perf | 5.950s | 966.420us | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 32.905m | 100.000ms | 20 | 50 | 40.00 |
| i2c_target_intr_smoke | 8.130s | 15.914ms | 41 | 50 | 82.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.408m | 10.049ms | 42 | 50 | 84.00 |
| i2c_target_fifo_reset_tx | 1.714m | 10.096ms | 41 | 50 | 82.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 18.147m | 600.000ms | 11 | 50 | 22.00 |
| i2c_target_stress_rd | 32.905m | 100.000ms | 20 | 50 | 40.00 | ||
| i2c_target_intr_stress_wr | 28.280s | 8.528ms | 16 | 50 | 32.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.860s | 2.016ms | 42 | 50 | 84.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 55.120m | 36.219ms | 39 | 50 | 78.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.070s | 1.488ms | 38 | 50 | 76.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.780s | 11.247ms | 47 | 50 | 94.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 38.156us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.690s | 34.055us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.760s | 240.541us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.760s | 240.541us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.770s | 84.163us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.730s | 23.176us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.750s | 311.578us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.130s | 65.748us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.770s | 84.163us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.730s | 23.176us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.750s | 311.578us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.130s | 65.748us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1159 | 1392 | 83.26 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.080s | 825.321us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.960s | 44.097us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.080s | 825.321us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 18.109m | 34.395ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 13.137m | 100.442ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 1299 | 1672 | 77.69 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 31 | 30 | 15 | 48.39 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.01 | 97.20 | 94.44 | 100.00 | 45.81 | 95.30 | 100.00 | 90.34 |
UVM_ERROR (i2c_scoreboard.sv:773) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 104 failures:
0.i2c_target_intr_stress_wr.36893603482497935192261667966702248638628183771730662374304926330861089192135
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest/run.log
UVM_ERROR @ 8528141348 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 8528141348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_intr_stress_wr.67294270057388999176557399032870784814742793126894837357446049310438272659809
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest/run.log
UVM_ERROR @ 8359038639 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 8359038639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
1.i2c_target_stress_all.103322444900386604628484427358831127930611895818673778353469709008783527388007
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 110143259 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 110143259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all.77234011812369646957560484602576348610836350544245987226906712399755940170140
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 159347884 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 159347884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
2.i2c_target_stress_wr.10477987564117263968849588011945298082836748434596451509468914995725336166243
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_wr/latest/run.log
UVM_ERROR @ 25955604575 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 25955604575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_wr.61020875912391832270787294109531205183041398359275715030962881897954931197911
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_wr/latest/run.log
UVM_ERROR @ 21314047784 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 21314047784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
2.i2c_target_stress_rd.59588399770411827211239237273778871289688801678645956644820719681505644249983
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_rd/latest/run.log
UVM_ERROR @ 18146264 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 18146264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_rd.62547232489878688617429027482834607143750672684368604332420058944459471886787
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_rd/latest/run.log
UVM_ERROR @ 203119164 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 203119164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
3.i2c_target_timeout.50004055073534468269617781911745347558203976139207841063256435400353991556453
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_timeout/latest/run.log
UVM_ERROR @ 14157285 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 14157285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_timeout.78409816652332078351250810515759198544058503161555942525132252997458389942354
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_timeout/latest/run.log
UVM_ERROR @ 55905442 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 55905442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 77 failures:
0.i2c_target_stretch.9953457742837270863110546854984844966551851133362374277790099233684369729704
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_ERROR @ 12658915 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 12658915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stretch.91097035488999954939290230020131761708309517890422251904709557897084070407902
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
UVM_ERROR @ 32190780 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 32190780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
0.i2c_target_stress_all.22784069159487790207986337699518115622877347815403010508182642563522170512973
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 46168165 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 46168165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all.104016580436674338074245231307910125954718833189218026257252433969820106825944
Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 23373103945 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 23373103945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
0.i2c_target_stress_all_with_rand_reset.65170325609935053897359637298311533048710420757890385296069055322586585948414
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 222971171 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 222971171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.45199597524189598040413789150324453427837908540114858296299347090594460548220
Line 418, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 35820502681 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 35820502681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
3.i2c_target_unexp_stop.58366577668532588317932726676957242119396452735419033652375183997310834238187
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 59805961 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 59805961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_unexp_stop.68903508557955844134398418291669546617592510593903553880466755383996525050814
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 6250212 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 6250212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
5.i2c_target_intr_stress_wr.114584397602925231467311331213194381709295696794744348403313044981143170182635
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest/run.log
UVM_ERROR @ 24753610 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 24753610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_intr_stress_wr.111783656442738672664017185520158211024612397594670912771461349829817067124885
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest/run.log
UVM_ERROR @ 31430101 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 31430101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:827) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:
0.i2c_host_stress_all_with_rand_reset.42994584518698567089960084749475075399841889289740766414580512737678260795019
Line 8181, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29025048184 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 29025048184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.15649914966149259948892887178664963365164911039406248043969577422941202301713
Line 1881, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55346207758 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 55346207758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 37 more failures.
1.i2c_target_stress_all_with_rand_reset.68284568219127414471549179038991620191153065489275378594252685928356154294733
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 105036760 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 105036760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.113732297783977738823567377579689754644121443488985702414829803960843012315394
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3244548255 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3244548255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 37 failures:
0.i2c_target_smoke.11311168778866964327687453271333412941949083419630509111604727427503294212179
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_smoke/latest/run.log
Job ID: smart:66dce634-9531-4395-b604-e25f2079619f
3.i2c_target_smoke.92555859590071159620179190821402919481229645432582957280138278224752646177628
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_smoke/latest/run.log
Job ID: smart:b7fd760c-c59a-434d-811e-3d9e0919a1d9
... and 5 more failures.
1.i2c_host_stress_all_with_rand_reset.24641514011262070323296857104069201830652975714237922252594536914191141542244
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:f55e5470-b910-4795-9120-1288cee9e7fd
11.i2c_host_stress_all_with_rand_reset.88608766092490384660918458781803080859606273372250560011755994298628015257906
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8a7c8011-34b5-449e-88b5-cd8023f7043c
... and 6 more failures.
2.i2c_host_stress_all.62601377356482354943054367358791760336425284681987152339749893986585421088364
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:5d8ae6ad-fa0b-42e5-9434-01e1c9d3092b
3.i2c_host_stress_all.105741532582519753311375902268666100921871158442970239374898904329275249505120
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
Job ID: smart:27161f9b-bf1e-4d2b-a881-4a81ec865e80
... and 8 more failures.
4.i2c_target_stress_rd.90018391573468415447658866695230423960617317996275413025747089987880535838619
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_rd/latest/run.log
Job ID: smart:0abfff3f-7f8b-4853-8dbc-8a78448c0f22
5.i2c_target_stress_rd.35311155639021703710143950324079470164380983174286106288038001004266113125791
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_rd/latest/run.log
Job ID: smart:f8835cdc-26d6-4850-aa58-9ecee7e53ae0
... and 8 more failures.
45.i2c_target_stretch.52368345586431503994443425324850119812441649484214173214946187523953833859029
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stretch/latest/run.log
Job ID: smart:5d1f55bd-0ab6-4d71-8130-65d03c4df75d
47.i2c_target_stretch.66545550237306522187100815133062774414980597141479664674231340225575251619987
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stretch/latest/run.log
Job ID: smart:e8e0a7bd-02f6-42f5-906a-a57fa3dcb0cb
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 27 failures:
0.i2c_target_stress_rd.12551129614366250823373625521988902202299113860929838912063228495030917625930
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_rd/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_rd.84962575554818765760609322178541694196137932054423136955288677027688180550057
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_rd/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
1.i2c_target_smoke.100535281453842376520693381148426103814022246667419014429330423328548672249423
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_smoke/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_smoke.79364372156389508178285346238249287039630935983147805002057484364227773490615
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_smoke/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
10.i2c_target_stress_wr.38706342355233420535032852962596296212111486236866529453909299394703785578115
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_wr/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.i2c_target_stress_wr.8644559469439123596735452282758561909738908616576823523408310232137104522123
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_wr/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:82) [target_smoke_vseq] wait timeout occurred! has 23 failures:
0.i2c_target_stress_wr.85035729553133842261906926668522050727183110332912817989248942042875088774126
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_wr/latest/run.log
UVM_FATAL @ 10792161479 ps: (i2c_target_smoke_vseq.sv:82) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10792161479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_wr.35905861276319596147600256022879828141112435954559262318157550790967557388283
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_wr/latest/run.log
UVM_FATAL @ 12171341533 ps: (i2c_target_smoke_vseq.sv:82) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 12171341533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
3.i2c_target_stress_all.35425218411061807614091131808327251347063023036608509126958921044172471170248
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 11862732448 ps: (i2c_target_smoke_vseq.sv:82) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 11862732448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.74290735172805138968383087864272147782704948865906653546742749853647248971680
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 20370295410 ps: (i2c_target_smoke_vseq.sv:82) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 20370295410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
7.i2c_target_stress_all_with_rand_reset.17517263132296497212103688010753808047378453961409169495410397629849723071158
Line 358, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13117447576 ps: (i2c_target_smoke_vseq.sv:82) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 13117447576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.i2c_target_stress_all_with_rand_reset.37065135812599102301127884415801546120218414350613444891374224689238746529316
Line 319, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12948849295 ps: (i2c_target_smoke_vseq.sv:82) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 12948849295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
18.i2c_target_intr_stress_wr.29959429198152310020988007257816744940906775604527482281745788725910824034704
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 10969359763 ps: (i2c_target_smoke_vseq.sv:82) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10969359763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_target_intr_stress_wr.74388094930297671470788709580651040942062458131293449819699276507442674599083
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 10523793654 ps: (i2c_target_smoke_vseq.sv:82) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10523793654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:55) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 12 failures:
2.i2c_host_fifo_watermark.42309990706686684163407094842859920636532150159631349398537016927328226912402
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest/run.log
UVM_ERROR @ 174265556 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 174265556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_host_fifo_watermark.53102397367847941352300617243341972789366752382376746933987563681753598286698
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_fifo_watermark/latest/run.log
UVM_ERROR @ 138938713 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 138938713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
4.i2c_host_stress_all_with_rand_reset.7957479181396568268877267011002690696050808430484084390127685594956294923269
Line 516, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 130374275 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 130374275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_host_stress_all_with_rand_reset.74837490457365175916415385834946623066888555553926104193373315997331491751436
Line 525, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 216318517 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 216318517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
10.i2c_host_stress_all.52051080088047362164799468437458830753966139502899372681543414332527615337874
Line 1065, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 44918922758 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 44918922758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_host_stress_all.69467343737942793236560445474313300089548900237623416488937384659998199868329
Line 514, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 125080879 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
UVM_INFO @ 125080879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 10 failures:
4.i2c_target_stress_all_with_rand_reset.50191156379539370966968590394578153721980287426363722590385274328697432905259
Line 377, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10808196513 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 10 [0xa])
UVM_INFO @ 10808196513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_target_stress_all_with_rand_reset.45157771089348977186045564893746197311306190053203377419872528793239394087533
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 69600101 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 28 [0x1c])
UVM_INFO @ 69600101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 6 failures:
4.i2c_target_smoke.26178519321586539543979545181416899570161706120717580677072183890808218245498
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_smoke/latest/run.log
Job ID: smart:f8f6ff0b-08e0-4c43-a323-cc6e205dd5a4
6.i2c_target_smoke.3762763796279085324696434487414459417092618582115609333895408863022094104287
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_smoke/latest/run.log
Job ID: smart:35bacdfc-d3db-4eb4-85d7-8aa876391f86
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 6 failures:
Test i2c_target_stress_wr has 1 failures.
9.i2c_target_stress_wr.46244823639496170202992226820245447110075445305344625947393724185770621490520
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_wr/latest/run.log
UVM_ERROR @ 20532573425 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (229 [0xe5] vs 232 [0xe8])
UVM_INFO @ 20532573425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_intr_stress_wr has 5 failures.
17.i2c_target_intr_stress_wr.108470600010281974381164364470329287724566504628509616692973209881658117628886
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_intr_stress_wr/latest/run.log
UVM_ERROR @ 7324936687 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (86 [0x56] vs 137 [0x89])
UVM_INFO @ 7324936687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_intr_stress_wr.43998093380671153406077323757551976296044615175882395424504805734590991739649
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest/run.log
UVM_ERROR @ 7616204023 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (120 [0x78] vs 17 [0x11])
UVM_INFO @ 7616204023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 5 failures:
6.i2c_target_stress_all_with_rand_reset.39861216959675057196597952951220660031435959209602736301373335067306727583893
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3457137614 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xfb118e14) == 0x0
UVM_INFO @ 3457137614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stress_all_with_rand_reset.60354483417190923378409072987991019185343026170866580818052562602768252936974
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 194010664 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x910f7014) == 0x0
UVM_INFO @ 194010664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred! has 5 failures:
8.i2c_target_stress_all.93386111044781681837968522891959490585395085257513469682388577551895089595029
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 23537305296 ps: (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 23537305296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stress_all.57541212733833189983869683387427648581863584299427897676838372702676126978019
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 21963594836 ps: (i2c_base_vseq.sv:1140) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 21963594836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_base_vseq.sv:961) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop has 4 failures:
Test i2c_target_timeout has 1 failures.
0.i2c_target_timeout.105440608113934043168985798973837604624484745367334627443059716973513478361879
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_timeout/latest/run.log
UVM_ERROR @ 134524806 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 134524806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_fifo_reset_acq has 1 failures.
3.i2c_target_fifo_reset_acq.72811351437482797668297390724428053791741121748596954548483265063849933387616
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_fifo_reset_acq/latest/run.log
UVM_ERROR @ 17927006 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 17927006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
16.i2c_target_stress_all.34238051572799843073510780275421419033964864624336822195695230452566112658143
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 93336813 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 93336813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_fifo_reset_tx has 1 failures.
41.i2c_target_fifo_reset_tx.77122170049679180665896121614342963725961767126766940818881564591406865995336
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest/run.log
UVM_ERROR @ 223889474 ps: (i2c_base_vseq.sv:961) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 223889474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 3 failures:
10.i2c_target_stress_all_with_rand_reset.32783969520344414516973705872884182664133039031446644570793783620982533265120
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3595052713 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (192 [0xc0] vs 92 [0x5c])
UVM_INFO @ 3595052713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.i2c_target_stress_all_with_rand_reset.94061597176541934229808988190263957639904824064545350308237574952750517571706
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 313444689 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 16 [0x10])
UVM_INFO @ 313444689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_glitch_vseq.sv:199) virtual_sequencer [i2c_glitch_vseq] timed out waiting for state: StretchAddr has 2 failures:
0.i2c_target_glitch.108417520683072901799396769259905361680182802605866048448263418759479530678305
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 2038629148 ps: (i2c_glitch_vseq.sv:199) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
UVM_INFO @ 2038629148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_glitch.677560412736933802784158986661415432906303044472564626844570596622231563761
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log
UVM_ERROR @ 905481842 ps: (i2c_glitch_vseq.sv:199) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
UVM_INFO @ 905481842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred! has 2 failures:
8.i2c_target_stress_all_with_rand_reset.11760919080251689390900583199485307867699465867417824880957377140594460442504
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1079040165 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
UVM_INFO @ 1079040165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stress_all_with_rand_reset.33491117688075535734360748586933659582373663609845349444174000144750934557519
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1348054654 ps: (i2c_driver.sv:275) [host_scl_pause_ctrl] wait timeout occurred!
UVM_INFO @ 1348054654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_i' has 1 failures:
5.i2c_target_stress_all_with_rand_reset.85593091411237887515546494972093943926959937657018413355459515350650337883262
Line 336, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 46381911909 ps: (i2c_fsm.sv:1511) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 46381911909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 1 failures:
30.i2c_target_stress_all_with_rand_reset.106136169758478579066865941345128517976879332878925984673621549220043177254763
Line 445, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 100441686832 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100441686832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---