I2C Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	2.571m	7.834ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	1.021m	14.803ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.710s	25.106us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.790s	72.659us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.810s	680.116us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.670s	63.358us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.480s	61.213us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.790s	72.659us	20	20	100.00
		i2c_csr_aliasing	1.670s	63.358us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	1.820s	72.363us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	55.606m	57.280ms	14	50	28.00
V2	host_perf	i2c_host_perf	59.145m	31.215ms	44	50	88.00
V2	host_override	i2c_host_override	0.730s	44.783us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.275m	31.864ms	44	50	88.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.269m	6.863ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.200s	351.220us	50	50	100.00
		i2c_host_fifo_fmt_empty	28.000s	545.705us	50	50	100.00
		i2c_host_fifo_reset_rx	9.640s	154.782us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.085m	28.951ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.130s	237.569us	0	50	0.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle			0	50	0.00
V2	target_error_intr	i2c_target_unexp_stop	9.350s	6.870ms	11	50	22.00
V2	target_glitch	i2c_target_glitch	4.210s	737.303us	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	45.070s	9.550ms	3	50	6.00
V2	target_perf	i2c_target_perf	1.150s	306.934us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.255m	1.806ms	50	50	100.00
		i2c_target_intr_smoke	7.850s	24.369ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.657m	10.026ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.961m	10.037ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.778m	600.000ms	12	50	24.00
		i2c_target_stress_rd	1.255m	1.806ms	50	50	100.00
		i2c_target_intr_stress_wr	1.259m	10.781ms	11	50	22.00
V2	target_timeout	i2c_target_timeout	7.820s	3.262ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	52.603m	17.261ms	39	50	78.00
V2	bad_address	i2c_target_bad_addr	5.070s	1.250ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.710s	684.743us	50	50	100.00
V2	alert_test	i2c_alert_test	0.670s	15.715us	50	50	100.00
V2	intr_test	i2c_intr_test	0.750s	60.066us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.000s	704.221us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.000s	704.221us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.710s	25.106us	5	5	100.00
		i2c_csr_rw	0.790s	72.659us	20	20	100.00
		i2c_csr_aliasing	1.670s	63.358us	5	5	100.00
		i2c_same_csr_outstanding	1.140s	64.546us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.710s	25.106us	5	5	100.00
		i2c_csr_rw	0.790s	72.659us	20	20	100.00
		i2c_csr_aliasing	1.670s	63.358us	5	5	100.00
		i2c_same_csr_outstanding	1.140s	64.546us	20	20	100.00
V2		TOTAL			1018	1392	73.13
V2S	tl_intg_err	i2c_tl_intg_err	2.140s	522.850us	20	20	100.00
		i2c_sec_cm	0.910s	255.719us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.140s	522.850us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	17.934m	19.754ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.583m	10.624ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
		TOTAL			1198	1672	71.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	31	30	18	58.06
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.87	97.30	94.04	100.00	45.81	94.80	100.00	90.13

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:773) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 109 failures:
- Test i2c_target_intr_stress_wr has 32 failures.
  - 0.i2c_target_intr_stress_wr.95576082582451247383570696101107909457931431481125512986123781775094533251920
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_ERROR @ 8451962219 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 8451962219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_intr_stress_wr.50400355202053108575605276610524466683355711294142482484557913662068103026951
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_ERROR @ 8276483403 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 8276483403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
- Test i2c_target_perf has 22 failures.
  - 0.i2c_target_perf.111417065478478698441353461996174932505225666214370597464142257974297074747717
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  44582886 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  44582886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.112381656676177303586261881080350263796527035527239355959895083675082261127752
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  28894164 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  28894164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
- Test i2c_target_stress_all has 21 failures.
  - 2.i2c_target_stress_all.52358341894884758783211833285792577949128350064736130977355934157035308581324
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 14192950791 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 14192950791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stress_all.114676486896200221811320423681777992893473565335609988800570976535829115367718
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 7736817081 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 7736817081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
- Test i2c_target_stress_wr has 19 failures.
  - 3.i2c_target_stress_wr.32337489849212422990361225182669150674554936993730051804493976028580005569104
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_wr/latest/run.log
```
  UVM_ERROR @ 23101470620 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 23101470620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.i2c_target_stress_wr.110676708504588755178336013151863178740235680816978585683461619210712493883370
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_wr/latest/run.log
```
  UVM_ERROR @ 23120290669 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 23120290669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
- Test i2c_target_stress_all_with_rand_reset has 15 failures.
  - 5.i2c_target_stress_all_with_rand_reset.13029335226553762573254602442843083339647624784775150963276869230309972712154
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  34261722 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  34261722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.i2c_target_stress_all_with_rand_reset.861945583027148729326179876441036789516967927613870238277267154337457609844
    Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2789703489 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2789703489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 79 failures:
- Test i2c_host_mode_toggle has 50 failures.
  - 0.i2c_host_mode_toggle.20687685495161426492662423349181555006409998632532732998711244199618061270793
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  Job ID: smart:7a623055-b1f1-4177-b5d7-8544370768d2
```
  - 1.i2c_host_mode_toggle.30042050777283467100721818510379065969650834728412306924833728939946683830908
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
```
  Job ID: smart:2503be53-7801-4413-be06-6284fab70be6
```
  - ... and 48 more failures.
- Test i2c_target_stretch has 11 failures.
  - 2.i2c_target_stretch.41380427883078873984705348670895871324255290106558770787721464507511861861982
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
```
  Job ID: smart:e0c491f1-19d6-4908-a3f8-917be7d4456c
```
  - 6.i2c_target_stretch.86667405412240099193459358263438244703247732833640136191641447011983377999711
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
```
  Job ID: smart:934011bc-d284-40bc-b913-54dad2b6e177
```
  - ... and 9 more failures.
- Test i2c_host_perf has 6 failures.
  - 9.i2c_host_perf.16982823822447962450176223941353284079391664086840253850870936640432695988515
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_perf/latest/run.log
```
  Job ID: smart:c3542891-2d5a-465c-9436-a252e998a0e8
```
  - 21.i2c_host_perf.23188734029765557740501379836114400812460347049883769710241800982915075777543
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_perf/latest/run.log
```
  Job ID: smart:a6aeee8b-2afb-4278-8f06-c92a2116efd5
```
  - ... and 4 more failures.
- Test i2c_host_stress_all has 8 failures.
  - 12.i2c_host_stress_all.10674318859891727030739219836898521558927862981230931572892882069486971738744
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:4e4c9566-c9a9-489a-97c6-53852e0459d3
```
  - 20.i2c_host_stress_all.101448588127173741374577593711742277854102936668424677055036731245111833333855
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:2e491289-cbfc-4c9e-8e79-5cf54e39f005
```
  - ... and 6 more failures.
- Test i2c_host_stress_all_with_rand_reset has 4 failures.
  - 12.i2c_host_stress_all_with_rand_reset.106560434167379341222693067479943990458259872628256875220374977091048075366507
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3e17b430-16cd-4d27-b92d-7800e7467393
```
  - 18.i2c_host_stress_all_with_rand_reset.84373035743670060618894053779379284318962362595753218200914377399772536878362
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a976a26a-16e8-4dbd-90c6-22b5ac8f9fb9
```
  - ... and 2 more failures.

UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 59 failures:

Test i2c_host_stretch_timeout has 29 failures.

0.i2c_host_stretch_timeout.6410924361076987016675919838285499785556229066498539219215219914888446864598
Line 310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @  34304871 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (4 [0x4] vs 15 [0xf])
  UVM_INFO @  34304871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stretch_timeout.58568055029158385368520714029036946495921565773086148328130281363988387234607
Line 358, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @  53170168 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (243 [0xf3] vs 27 [0x1b])
  UVM_INFO @  53170168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 27 more failures.

Test i2c_host_stress_all has 18 failures.

0.i2c_host_stress_all.3584966753593924361959372716845950889387799103998415895460941501199463369130
Line 321, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 6091463133 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (12 [0xc] vs 2 [0x2])
  UVM_INFO @ 6091463133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all.63799554117039603070744570501197639564278147120228764703713581485329869254594
Line 422, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 520516022 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (161 [0xa1] vs 32 [0x20])
  UVM_INFO @ 520516022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 16 more failures.

Test i2c_host_stress_all_with_rand_reset has 12 failures.

1.i2c_host_stress_all_with_rand_reset.4248999676294806133713535826692943672388391161736001704196551743605224171291
Line 312, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  90471463 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (2 [0x2] vs 11 [0xb])
  UVM_INFO @  90471463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stress_all_with_rand_reset.99118873493758125409920348733470962423637734212082121751437154183407686811473
Line 2567, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 65343544273 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (72 [0x48] vs 8 [0x8])
  UVM_INFO @ 65343544273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_ERROR (i2c_base_vseq.sv:968) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 51 failures:
- Test i2c_target_unexp_stop has 38 failures.
  - 0.i2c_target_unexp_stop.20860488052575517589734170324505963897309798304327088968257151029810691014882
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 4038586607 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 4038586607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_unexp_stop.30224071457747368149192486082000130925465245256867648970035600767890297464353
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 2748356970 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 2748356970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 36 more failures.
- Test i2c_target_stress_all has 13 failures.
  - 0.i2c_target_stress_all.106452789941721171468353703731355265047092018001276465687291124224416588449207
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 4303693927 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 4303693927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.i2c_target_stress_all.87071332956504790477904821891044161272087040455215596819104478099492764789403
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 4656383525 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 4656383525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 41 failures:
- Test i2c_target_stress_all has 9 failures.
  - 1.i2c_target_stress_all.48948574162939080566591263998768883849260647788084841006133835876341807059433
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 1058592620 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 1058592620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.i2c_target_stress_all.44461364058210206265220980583928945409216320090152623543246270943303378962188
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  33275490 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  33275490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
- Test i2c_target_stress_all_with_rand_reset has 8 failures.
  - 2.i2c_target_stress_all_with_rand_reset.32527872448143472777662851441801236524023036627454009757028682209891192612612
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  24797479 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  24797479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stress_all_with_rand_reset.36366569501222242572364767717387623592533258462608140536535193023296248056883
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  23623754 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  23623754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
- Test i2c_target_perf has 24 failures.
  - 3.i2c_target_perf.6722507491223459308022304186731908372896865366852630008923015715428048002478
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  22994618 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  22994618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_perf.25854230333635001612035573207841202706404482718494425138491462512719446097441
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  31318921 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  31318921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.

UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:66) [i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == * (* [*] vs * [*]) has 40 failures:

Test i2c_host_stress_all_with_rand_reset has 11 failures.

0.i2c_host_stress_all_with_rand_reset.21908281615552130249953498144981325073236465047843680857206362099122898515054
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 151138394 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (3 [0x3] vs 1 [0x1])
  UVM_INFO @ 151138394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_host_stress_all_with_rand_reset.51426673019122590955431253879140545791460590233256581523237685112667183549177
Line 572, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 23220510870 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (126 [0x7e] vs 1 [0x1])
  UVM_INFO @ 23220510870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test i2c_host_stretch_timeout has 21 failures.

2.i2c_host_stretch_timeout.42011921682283735676565505776592075501718148254867119264709508059658681389862
Line 386, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @ 342251064 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (207 [0xcf] vs 1 [0x1])
  UVM_INFO @ 342251064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_host_stretch_timeout.76817784153576334309281658139099156760616268623585223450054883817261557443025
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @  54975587 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (12 [0xc] vs 1 [0x1])
  UVM_INFO @  54975587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 19 more failures.

Test i2c_host_stress_all has 8 failures.

4.i2c_host_stress_all.113832336915706489410616885415535065801691048762924710940513279872334059563428
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @  23778864 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @  23778864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_host_stress_all.80510232444616325701628641952820987922665658707031787597223693389708166304395
Line 5452, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 21382139358 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (41 [0x29] vs 1 [0x1])
  UVM_INFO @ 21382139358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:

Test i2c_target_stress_all_with_rand_reset has 13 failures.

0.i2c_target_stress_all_with_rand_reset.6349129448673421275683505175724827051269528179426745594970779443618210205833
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9746898810 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9746898810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.60354298531814196206650419959397982498621342415565876868950821481864567189109
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 107662493 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107662493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Test i2c_host_stress_all_with_rand_reset has 22 failures.

4.i2c_host_stress_all_with_rand_reset.23806753531243497432325406261290683441834276551319063952802590604068142477775
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1245444954 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1245444954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_host_stress_all_with_rand_reset.12196584662810987231431728901127013194008643022282577575291686560392008316350
Line 2596, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11728403617 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11728403617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 20 more failures.

UVM_FATAL (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred! has 25 failures:
- Test i2c_target_stress_wr has 16 failures.
  - 0.i2c_target_stress_wr.27372461565632550701141849384742138413503397773689815684866394132581829319413
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_wr/latest/run.log
```
  UVM_FATAL @ 13939571403 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 13939571403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_stress_wr.18770131446112227673402671648646890426685552601293723092246295579226486000003
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_wr/latest/run.log
```
  UVM_FATAL @ 15997116842 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 15997116842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
- Test i2c_target_intr_stress_wr has 3 failures.
  - 10.i2c_target_intr_stress_wr.34565548514933680804943131985022553452527970778894451311112011101457740760881
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 13261992012 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 13261992012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.i2c_target_intr_stress_wr.19154357175011122698774023108925206392012450816813526803108265009987978856715
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 10451786519 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10451786519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test i2c_target_stress_all_with_rand_reset has 5 failures.
  - 13.i2c_target_stress_all_with_rand_reset.96232442985518437296326124047062345980559603198418326060951952773734052215900
    Line 314, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 20316452436 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 20316452436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.i2c_target_stress_all_with_rand_reset.102942347593902513533517353161571051878520039516914929138001921607959399062997
    Line 285, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12377490450 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 12377490450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
- Test i2c_target_unexp_stop has 1 failures.
  - 35.i2c_target_unexp_stop.64208674699401464711989757679718996967626838917657290402982177789584722806766
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 14929251364 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 14929251364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:55) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 9 failures:

Test i2c_host_fifo_watermark has 6 failures.

5.i2c_host_fifo_watermark.42056003489859878311984367792920256254625171930324396954583887355072024945791
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest/run.log

  UVM_ERROR @ 135324400 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 135324400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.i2c_host_fifo_watermark.21525087878202535444255339148085551357572617214797068890421559223198652922141
Line 510, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_fifo_watermark/latest/run.log

  UVM_ERROR @ 439999280 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 439999280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test i2c_host_stress_all has 2 failures.

22.i2c_host_stress_all.101837018377558275054972570938831018841359117215325542839730443151738511852319
Line 1428, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 332502732 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 332502732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.i2c_host_stress_all.91067832517900918384386994337386197234470205259017301597065482095810161610712
Line 9930, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 7726979475 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 7726979475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_stress_all_with_rand_reset has 1 failures.

38.i2c_host_stress_all_with_rand_reset.14139390512734554419487839387146957752818878936502266198987235711699150783569
Line 516, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 105226326 ps: (i2c_host_fifo_watermark_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 2 (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 105226326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 6 failures:
- Test i2c_target_stress_all has 2 failures.
  - 7.i2c_target_stress_all.95782795031892183372624126682581601922458753062946903732326232059892734708071
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 1459327477 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 6 [0x6])
  UVM_INFO @ 1459327477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.i2c_target_stress_all.27014249872650075661873647410193313097132866026604785603352846072503424409003
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 11626547645 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 4 [0x4])
  UVM_INFO @ 11626547645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 7.i2c_target_stress_all_with_rand_reset.67493942904759974844854405428073991766650741209722019596611728585731463247176
    Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1146079025 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (7 [0x7] vs 4 [0x4])
  UVM_INFO @ 1146079025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.i2c_target_stress_all_with_rand_reset.86485191686031552123958641275297278195460898271527631460817575678343422263338
    Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8970957414 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (21 [0x15] vs 19 [0x13])
  UVM_INFO @ 8970957414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (i2c_base_vseq.sv:968) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop has 6 failures:

Test i2c_target_stress_all has 2 failures.

9.i2c_target_stress_all.89095059165274324747090898551190342089501336740452115126007008819446878511330
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 748716874 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
  UVM_INFO @ 748716874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.i2c_target_stress_all.48264777265002719808402399683425386857962409515708053841030718184800901307669
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 3085773393 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
  UVM_INFO @ 3085773393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_target_perf has 4 failures.

29.i2c_target_perf.107596158875115871400687221660766419805365176111290349544585448092318359533184
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_perf/latest/run.log

  UVM_ERROR @  59181616 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
  UVM_INFO @  59181616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.i2c_target_perf.110950158050257932427388481911862367640455471464754808778628476051040010851712
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_perf/latest/run.log

  UVM_ERROR @   7109452 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
  UVM_INFO @   7109452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 5 failures:
- Test i2c_target_intr_stress_wr has 3 failures.
  - 8.i2c_target_intr_stress_wr.15124471321561519252827230184733112066883756676420843953165513611095375465200
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_ERROR @ 8808525378 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (165 [0xa5] vs 96 [0x60])
  UVM_INFO @ 8808525378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.i2c_target_intr_stress_wr.10588305180611952005019340691610296238185991277696163330595412652111359719193
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_ERROR @ 9812509139 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (60 [0x3c] vs 52 [0x34])
  UVM_INFO @ 9812509139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test i2c_target_stress_wr has 2 failures.
  - 32.i2c_target_stress_wr.92465022066712725438907705510342120571999278187801399441847909848763617008028
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stress_wr/latest/run.log
```
  UVM_ERROR @ 22455186649 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (2 [0x2] vs 97 [0x61])
  UVM_INFO @ 22455186649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.i2c_target_stress_wr.57693925595257150186399376448304840391942234843746777239615106336522682844788
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_wr/latest/run.log
```
  UVM_ERROR @ 21940521070 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (214 [0xd6] vs 76 [0x4c])
  UVM_INFO @ 21940521070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 5 failures:
- Test i2c_target_stress_all_with_rand_reset has 5 failures.
  - 10.i2c_target_stress_all_with_rand_reset.63355611370154139076224438362015828509505016218116266511102715124148334647520
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 17823278511 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xc2b5e494) == 0x0
  UVM_INFO @ 17823278511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.i2c_target_stress_all_with_rand_reset.73297515956492860243604668238551837951117901213424829837680857152967559538538
    Line 306, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 25807901493 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xeaf4ba94) == 0x0
  UVM_INFO @ 25807901493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (i2c_glitch_vseq.sv:197) virtual_sequencer [i2c_glitch_vseq] timed out waiting for state: StretchAddr has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.94468323524590470283555302342050414056694257113318649968915405552500498229199
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 737303062 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
  UVM_INFO @ 737303062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.89676988598342260587341491364572049248516575487071013662475770701010564743269
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 2362522097 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
  UVM_INFO @ 2362522097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_stress_wr has 1 failures.
  - 35.i2c_target_stress_wr.27945370769288240874244385233371456544364009830302620980451518657754181714349
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_wr/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1147) [stop_interrupt_handler] wait timeout occurred! has 1 failures:
- Test i2c_target_intr_stress_wr has 1 failures.
  - 49.i2c_target_intr_stress_wr.20713396781144608477589548616142846918651477112434504694555442806292347613571
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 10781141755 ps: (i2c_base_vseq.sv:1147) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10781141755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```