70ad420931| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.609m | 6.543ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 57.410s | 1.449ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.810s | 62.314us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.840s | 26.337us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.750s | 1.896ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.810s | 254.135us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.590s | 59.001us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.840s | 26.337us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.810s | 254.135us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 154 | 155 | 99.35 | |||
| V2 | host_error_intr | i2c_host_error_intr | 2.250s | 76.562us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 55.174m | 42.572ms | 10 | 50 | 20.00 |
| V2 | host_perf | i2c_host_perf | 50.475m | 6.567ms | 46 | 50 | 92.00 |
| V2 | host_override | i2c_host_override | 0.710s | 69.632us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.572m | 4.289ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.697m | 8.637ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.210s | 115.642us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 24.600s | 862.585us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 11.420s | 204.631us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.326m | 2.642ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 6.690s | 1.447ms | 0 | 50 | 0.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 9.787m | 600.000ms | 0 | 50 | 0.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 7.570s | 2.670ms | 9 | 50 | 18.00 |
| V2 | target_glitch | i2c_target_glitch | 3.460s | 571.687us | 0 | 2 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 1.150m | 16.193ms | 1 | 50 | 2.00 |
| V2 | target_perf | i2c_target_perf | 0.950s | 246.569us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.329m | 13.350ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.770s | 5.805ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.608m | 10.074ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.080m | 10.040ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 36.760s | 17.341ms | 11 | 50 | 22.00 |
| i2c_target_stress_rd | 1.329m | 13.350ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 15.020s | 7.040ms | 14 | 50 | 28.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.410s | 11.245ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 57.403m | 31.513ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.880s | 1.297ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.420s | 635.481us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.690s | 23.241us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.800s | 15.781us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.820s | 547.092us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.820s | 547.092us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.810s | 62.314us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.840s | 26.337us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.810s | 254.135us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.170s | 50.522us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.810s | 62.314us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.840s | 26.337us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.810s | 254.135us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.170s | 50.522us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1027 | 1392 | 73.78 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.340s | 433.813us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.950s | 221.697us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.340s | 433.813us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 15.096m | 12.681ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 4.432m | 6.958ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 1206 | 1672 | 72.13 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 31 | 30 | 19 | 61.29 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.53 | 97.38 | 90.88 | 97.65 | 43.87 | 94.77 | 98.44 | 89.71 |
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))' has 95 failures:
0.i2c_target_stress_wr.64722314850086734183792378136257913579446501787535415238253656771486228770921
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 1678040338 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 1678040338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_wr.40011582955487680523570957687227917844538238112592274522862418502607755955762
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 589196741 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 589196741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 37 more failures.
1.i2c_target_intr_stress_wr.39077158827260336496963060345550008300867009564935409671030347299176877846581
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 2108054044 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 2108054044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_intr_stress_wr.23321693938576029373623407163399870625893120009007556901751761939127882393301
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 1365060894 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 1365060894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
2.i2c_target_stress_all.101572714020038239018956901598993538394661790351244961354363667452824347181617
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 7022658594 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 7022658594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all.91169264099999394224778997653188481181815410476645510980534039890952460169554
Line 290, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 16193196706 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 16193196706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
8.i2c_target_stress_all_with_rand_reset.16225374267606222429985087786893855965453557577570997895105892462665895581008
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 772957839 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 772957839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_stress_all_with_rand_reset.50594375677977311932533350927489183420357497558029142893995083338361166635144
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 1716289616 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 1716289616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 71 failures:
Test i2c_host_mode_toggle has 49 failures.
0.i2c_host_mode_toggle.5158400654025138097167259814565735094068542699814372689051956926220952476478
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
Job ID: smart:9644cdee-524f-4ad1-8711-078af9584527
1.i2c_host_mode_toggle.79652845943621261891043147674196440371047150176327563705683724495139745212214
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
Job ID: smart:4df25e83-bb9f-42f7-9de6-64305c94e384
... and 47 more failures.
Test i2c_host_stress_all has 7 failures.
2.i2c_host_stress_all.36784776323376134064608092920856041736142854389015815812670621403860544693522
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:eec623db-58c0-4ae4-a2d9-6b4cf6f8faef
8.i2c_host_stress_all.82052393757754503361233908520886422666022629598737569415969361903620239694237
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
Job ID: smart:1bb701f1-ea22-4582-9f18-11d0cbd89c52
... and 5 more failures.
Test i2c_host_stress_all_with_rand_reset has 8 failures.
4.i2c_host_stress_all_with_rand_reset.21695703988534521076928070646739571024019596463595054501765923361595437917554
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:a9c1f2f5-18b0-4624-a6f9-d8fafb61ae9e
7.i2c_host_stress_all_with_rand_reset.85904711973819221188940103016541076119037615946849417279981621663895173193626
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:0e593e2e-d790-46b5-bf1c-00af58b3caef
... and 6 more failures.
Test i2c_target_stretch has 4 failures.
8.i2c_target_stretch.64618459992827262000696736496485997529563669244691899472644082664703595888102
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stretch/latest/run.log
Job ID: smart:d2190ca9-232a-4b70-b598-feec09d16c0f
19.i2c_target_stretch.99018805134408785767337354055795792286977546460495997580682615453805474020345
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stretch/latest/run.log
Job ID: smart:fa0119c6-0636-4e99-9be9-876948427a3f
... and 2 more failures.
Test i2c_host_perf has 2 failures.
15.i2c_host_perf.58418943380022553689620597026577338870443643101961433896038592121659837199432
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_perf/latest/run.log
Job ID: smart:13ef1f39-67b5-4114-818f-6ca10da28933
21.i2c_host_perf.82166939970976804049318404173528932055030102071450203272999428360569502207638
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_perf/latest/run.log
Job ID: smart:c1af8aa7-0ba9-48b0-8cd4-1d2b307048b7
... and 1 more tests.
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 69 failures:
0.i2c_host_stretch_timeout.11928742768594364652278185657301544418843628067726467671450354012958703919442
Line 410, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 371486128 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (4 [0x4] vs 2 [0x2])
UVM_INFO @ 371486128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stretch_timeout.93798534563502320256868763593770344036035982765543530316736924926309116376181
Line 382, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 194034208 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (296 [0x128] vs 33 [0x21])
UVM_INFO @ 194034208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
1.i2c_host_stress_all.10534369961283255275586112376664031756707481936191795993426675037020923066183
Line 4047, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 4128043256 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (81 [0x51] vs 9 [0x9])
UVM_INFO @ 4128043256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_host_stress_all.65880650037572544523790146809426184351681383757833171471354672675908349467979
Line 2591, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 3398543566 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (54 [0x36] vs 6 [0x6])
UVM_INFO @ 3398543566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
5.i2c_host_stress_all_with_rand_reset.87164715714181292057763400002167657999367383014567281236050513399425402615995
Line 3725, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 34636765853 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (12 [0xc] vs 2 [0x2])
UVM_INFO @ 34636765853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_host_stress_all_with_rand_reset.108115879960296599027420999353161625135453502493568393209429331472777966349308
Line 323, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1331478560 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (11 [0xb] vs 2 [0x2])
UVM_INFO @ 1331478560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (i2c_base_vseq.sv:968) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 55 failures:
0.i2c_target_unexp_stop.12956242535009739826660661299039121969143898566889355813976095185459967861739
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 853677156 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 853677156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.47701959523798364869932516048348653684776807576977363863953955433690458465214
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3340682848 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3340682848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 39 more failures.
12.i2c_target_stress_all.42277285704357350508757722979742123798664565016781788772021128725628400528780
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 3598034290 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3598034290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stress_all.1945383545585175453764609307565190229367463494031033495679226700393030908214
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 929720125 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 929720125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 52 failures:
1.i2c_target_perf.79047838190686640519715494690483307828184358491061358058657815995091162403897
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 18021872 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 18021872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_perf.11353018320504837781119184063684733758291083900803089107982039856635054128826
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
UVM_ERROR @ 97180930 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 97180930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
1.i2c_target_stress_all.14984478606117192839899081867788048623141936385874104999607975358417557902734
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 32745397 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 32745397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all.80301186374650857413981024525898463096031802418089027434125423263810340565770
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 47860940 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 47860940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
3.i2c_target_stress_all_with_rand_reset.13171638482514190907566544021451096256898887742070893848701775309182154042855
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 52792023 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 52792023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.109033861224800573816979289782001963433562476280664337768863480512688347190783
Line 320, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2456062957 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 2456062957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
0.i2c_target_stress_all_with_rand_reset.77407100479591732811664377343618841420015740795635067209436651271813428837751
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9978099828 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9978099828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.38875037997588165262817281322388317705362350236576583713340477685013243774018
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 669141663 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 669141663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
1.i2c_host_stress_all_with_rand_reset.89702869343664524667700368876215810532103302580091260140620103688387193012002
Line 7169, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29471243783 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 29471243783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.68762293239992951912804642331763846475361283334519025816738714118343835200877
Line 3074, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9866200029 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9866200029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:66) [i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == * (* [*] vs * [*]) has 32 failures:
0.i2c_host_stress_all.100874997915101625075544983343229634333597259061322600028126955022928315954541
Line 4412, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 2957637815 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (40 [0x28] vs 1 [0x1])
UVM_INFO @ 2957637815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_stress_all.69925863538733849034879435058480926934502487267508457343313788065320316354574
Line 6609, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 15701301867 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (138 [0x8a] vs 1 [0x1])
UVM_INFO @ 15701301867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
0.i2c_host_stress_all_with_rand_reset.17345112933503355233963535610150429019211963271012959023354300652237286136298
Line 411, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8360342633 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (45 [0x2d] vs 1 [0x1])
UVM_INFO @ 8360342633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_host_stress_all_with_rand_reset.2355832628142619748436863349984384345555754687282070251801925699146135912666
Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 61135314 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (81 [0x51] vs 1 [0x1])
UVM_INFO @ 61135314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
2.i2c_host_stretch_timeout.34919434601101649519824802152902267799607184605188666317038526460424471288553
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 124445241 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 124445241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_host_stretch_timeout.71806462066545711554813320378040956609320340218424715328152479973786245632387
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 27987106 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (46 [0x2e] vs 1 [0x1])
UVM_INFO @ 27987106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (i2c_scoreboard.sv:773) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 24 failures:
0.i2c_target_perf.91676014589838594927036551968086152354031705757260191662439964579538928447554
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 149756157 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 149756157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_perf.20441769619193202760205162307006917183758959111910116204195659411404214337800
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_perf/latest/run.log
UVM_ERROR @ 246569337 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 246569337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
0.i2c_target_stress_all.84999712833320449879915272780458098704954649773848045544412949585110634180111
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 20301924 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 20301924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.114891073526196352815328966773883759214173852256831976912047406714512758417465
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 8566710297 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 8566710297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
1.i2c_target_stress_all_with_rand_reset.28614740660103218032443136507020600722871780667063309943116556539040262092891
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3435865957 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3435865957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.71390567485274682111493441470946329691597057025755211613784628891879997034815
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 248198204 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 248198204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_base_vseq.sv:968) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop has 7 failures:
Test i2c_target_perf has 2 failures.
13.i2c_target_perf.34728656979390866946574040274798941357813938251430676242084108835445337156470
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_perf/latest/run.log
UVM_ERROR @ 5482293 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 5482293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.i2c_target_perf.86858083694980102907240086576447146156362261040017025632254967292213637922507
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_perf/latest/run.log
UVM_ERROR @ 106479392 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 106479392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 5 failures.
16.i2c_target_stress_all.112760025711764062144123810082868013488317796482475069081116099325787069947464
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 4563983449 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 4563983449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_target_stress_all.75477984588730014476478640838009676954620284293776651004305878140110602260411
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 10254745186 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 10254745186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
11.i2c_target_stress_all_with_rand_reset.97493671834851584788406713777655990626375847721019864501041792131320091633517
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1546592137 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1546592137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stress_all_with_rand_reset.21113794320973622046643212558959171631651178578939736786981978747248100428714
Line 302, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 17608265961 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 17608265961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred! has 4 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
4.i2c_target_stress_all_with_rand_reset.41601519186172172476855530592795680727387482233071712442350660369504006225643
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10458818898 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10458818898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.69328605083387707569706281028623897835293130341165353711938472919694131774113
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10373540239 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10373540239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 2 failures.
34.i2c_target_stress_all.109484495282273508256438077177090685180889474168759034466487226924087496010346
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 21273095816 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 21273095816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.i2c_target_stress_all.57568966197268477070944525417000643418690983075821657712415365548309293236090
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 11747615649 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 11747615649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 4 failures:
15.i2c_target_stress_all_with_rand_reset.62236012366286586947151618963521583014871086829923843804341245495475132522806
Line 285, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3793695655 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 5 [0x5])
UVM_INFO @ 3793695655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.i2c_target_stress_all_with_rand_reset.66537496650605353629529210565804695723236545457531462087024282634683422023284
Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 895226401 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 6 [0x6])
UVM_INFO @ 895226401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
24.i2c_target_stress_all.73930535224319000116044636589358369193245570629980338183243014471970751917420
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 7141544679 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 2 [0x2])
UVM_INFO @ 7141544679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_glitch_vseq.sv:197) virtual_sequencer [i2c_glitch_vseq] timed out waiting for state: StretchAddr has 2 failures:
0.i2c_target_glitch.99430920379631793647179701243232633601364923689581640050547761542878865511166
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 1944301999 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
UVM_INFO @ 1944301999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_glitch.84461246703817622168578565169509234471560613569752924595482476332419047849847
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log
UVM_ERROR @ 571687092 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
UVM_INFO @ 571687092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
27.i2c_target_stress_all_with_rand_reset.73926210201132438191743188897322550409107556375217554454264696026723335292963
Line 324, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21889631948 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 21889631948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.i2c_target_stress_all_with_rand_reset.51734217180822377081160865358062858412769035632020708915145687759853896446320
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1413306318 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1413306318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 2 failures:
28.i2c_target_stress_all_with_rand_reset.10737537416447421778025824611879612372332810715146884397649825295989615889486
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13828350178 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xf69e4094) == 0x0
UVM_INFO @ 13828350178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.i2c_target_stress_all_with_rand_reset.47561728592825316916452013730685320481491430540483931120394300052213211183060
Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 20785110805 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xb2bde514) == 0x0
UVM_INFO @ 20785110805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
4.i2c_csr_bit_bash.33520567431781096668677827262862849572084776090236714833455516535224102575754
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 1896145602 ps: (i2c_fifos.sv:309) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 1896145602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_i' has 1 failures:
14.i2c_host_perf.4409438605557485559820596682687874271743498779555398362707052462464426808575
Line 873, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_perf/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 858646488 ps: (i2c_fsm.sv:1628) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 858646488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
23.i2c_host_mode_toggle.30469834152434226100309080899712869009147965295808119202211775710220614349744
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
40.i2c_host_perf.60585857787546102757358791617969246374874935114572523226446286352720322198925
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_perf/latest/run.log
UVM_ERROR @ 7497057441 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value