b111fbcef3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.428m | 7.629ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 53.330s | 1.311ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 41.613us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.780s | 25.763us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.530s | 117.613us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.620s | 36.909us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.640s | 175.367us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.780s | 25.763us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.620s | 36.909us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 1.930s | 38.152us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 43.939m | 254.927ms | 15 | 50 | 30.00 |
| V2 | host_perf | i2c_host_perf | 50.082m | 26.514ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.710s | 165.019us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.352m | 55.120ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.775m | 9.239ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.280s | 130.216us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 27.080s | 779.404us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 9.990s | 355.410us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.022m | 9.718ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 6.430s | 127.051us | 0 | 50 | 0.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 9.708m | 600.000ms | 0 | 50 | 0.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 7.460s | 1.110ms | 6 | 50 | 12.00 |
| V2 | target_glitch | i2c_target_glitch | 4.190s | 671.579us | 0 | 2 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 34.970s | 27.679ms | 1 | 50 | 2.00 |
| V2 | target_perf | i2c_target_perf | 0.910s | 183.962us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.133m | 6.136ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 7.760s | 1.506ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.723m | 10.069ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.759m | 10.121ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 26.100s | 12.774ms | 8 | 50 | 16.00 |
| i2c_target_stress_rd | 1.133m | 6.136ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 16.660s | 7.273ms | 16 | 50 | 32.00 | ||
| V2 | target_timeout | i2c_target_timeout | 7.990s | 1.359ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 59.515m | 41.575ms | 42 | 50 | 84.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.250s | 1.221ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.270s | 1.143ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.690s | 15.995us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.710s | 52.107us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.520s | 243.354us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.520s | 243.354us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 41.613us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.780s | 25.763us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.620s | 36.909us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.100s | 73.923us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 41.613us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.780s | 25.763us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.620s | 36.909us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.100s | 73.923us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1026 | 1392 | 73.71 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.290s | 532.228us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.970s | 68.131us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.290s | 532.228us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 16.241m | 17.783ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 3.348m | 12.639ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 1206 | 1672 | 72.13 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 31 | 30 | 19 | 61.29 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.31 | 97.09 | 91.06 | 97.65 | 42.58 | 94.36 | 98.44 | 90.02 |
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))' has 101 failures:
0.i2c_target_stress_wr.108726584045701284985603287129312995698138101829310937887970100216097446662767
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 914044745 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 914044745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_wr.100287632505445154534398701416499599308415535635691997937613087986755808559419
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 3139512754 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 3139512754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 40 more failures.
0.i2c_target_intr_stress_wr.6864979568764944019618307615883505905083585366768635926181882265472231237021
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 2791122636 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 2791122636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_intr_stress_wr.11278876060577412612846909575742881873738645728016355548991468944651043006951
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 1584754599 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 1584754599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
1.i2c_target_stress_all.56896835065402098437002797339525478598330999210371405214816840105284673272443
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 28240636201 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 28240636201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.60728075865093751328146627195565040826287448421361415116931774043717211054263
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 6805779982 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 6805779982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
5.i2c_target_stress_all_with_rand_reset.72086738342476965888937722611394148720925137920332386324186940285586889589920
Line 290, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 5254054860 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 5254054860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.52391977071464043966966246566019123091480208725931940343488897354622329518646
Line 319, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 56254612605 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 56254612605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 67 failures:
Test i2c_host_mode_toggle has 49 failures.
0.i2c_host_mode_toggle.10960023538062744560109444534536725393872443375688305568870679095269667518742
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
Job ID: smart:64fdd1a2-6e31-47d8-a4fc-3b14ea61527c
1.i2c_host_mode_toggle.28361743625865696204936235883001698643235215396161641625488878482036100750119
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
Job ID: smart:19c1d08f-33c4-48a1-8b97-a31106ce8dc7
... and 47 more failures.
Test i2c_target_stretch has 8 failures.
2.i2c_target_stretch.56919795106285564396868173647108329017403351679131530164538466941589574078332
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
Job ID: smart:15fc7553-bdb0-4f21-965a-24f10c71d050
5.i2c_target_stretch.95073903818734768074349201336295930783216792027687855122998965986059081666673
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
Job ID: smart:e42aa2cd-371b-4e53-8dfb-638cc30cb0c2
... and 6 more failures.
Test i2c_host_stretch_timeout has 1 failures.
4.i2c_host_stretch_timeout.54932692066814584417347194187184958432623071267602589383788877138963958131051
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stretch_timeout/latest/run.log
Job ID: smart:6b7b9e43-2e1f-4bbe-9403-a24b28a2f1f1
Test i2c_host_perf has 2 failures.
6.i2c_host_perf.15591841556726616039190962931146360210992795359698163756156160428707907471375
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_perf/latest/run.log
Job ID: smart:bd571165-2d31-448d-a179-c052a2cffc6b
33.i2c_host_perf.75766047370918692282936257612790864712293883671897519818486837201837178060931
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_host_perf/latest/run.log
Job ID: smart:ec6dba65-af37-4bda-bccd-ccd7c734862a
Test i2c_host_stress_all has 5 failures.
7.i2c_host_stress_all.78264344061463028542107344639387850260593559472003474810717573577580007836188
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
Job ID: smart:5f718c80-ec41-479e-8370-e1d4ff0f8176
14.i2c_host_stress_all.838326390896944089330315404345992113684142129179408583174468801438751996404
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
Job ID: smart:eabc5cc6-9e35-4ff8-8738-2e6564bd60fe
... and 3 more failures.
... and 1 more tests.
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 62 failures:
0.i2c_host_stretch_timeout.77791455858342790299337282555983813694545972038785140921882501739833209529820
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 5077001 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (18 [0x12] vs 2 [0x2])
UVM_INFO @ 5077001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stretch_timeout.50194492889479400443926295865927335271692569912739556572026962907737123423743
Line 286, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 38414179 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (4 [0x4] vs 9 [0x9])
UVM_INFO @ 38414179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
0.i2c_host_stress_all.9174445975879230532436305736055420486464877994503050479831973635448494476251
Line 3187, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 5066723268 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (20 [0x14] vs 4 [0x4])
UVM_INFO @ 5066723268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_host_stress_all.35283652491298709597036848912210503039983735800161412511233295563956034958282
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 24835355 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (12 [0xc] vs 2 [0x2])
UVM_INFO @ 24835355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
0.i2c_host_stress_all_with_rand_reset.30910948215319396184700149155750735445386825293658088954990043495581161779658
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 72954493 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (14 [0xe] vs 4 [0x4])
UVM_INFO @ 72954493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.19611789776892230316641854191158566139990437675850015076428571170307748439169
Line 3927, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8508466694 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (26 [0x1a] vs 5 [0x5])
UVM_INFO @ 8508466694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_base_vseq.sv:968) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 59 failures:
0.i2c_target_unexp_stop.92725775310534331682345636123430044054348979086500123981111203575254131490046
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 4528611046 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 4528611046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.50556026509608788047757969334311275556411329421706880590453030542697497070420
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3162363563 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3162363563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 40 more failures.
3.i2c_target_stress_all.27101141429928576709583422034106143489888894213792877034728585541515134757632
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 8827461654 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 8827461654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.102974564136393706895726399249071032205452044484326237396901388693992659676873
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1547799478 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1547799478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 52 failures:
0.i2c_target_perf.101476757086535425462222027649062653669564977939113461793531734496058073532176
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 14972657 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 14972657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.101875026265390334231807693224092163616067549355913740962009588347835045366544
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 17953755 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 17953755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 35 more failures.
0.i2c_target_stress_all.26955598991874017391558933874140627714322386033423779622675055769737840504547
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 40042591 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 40042591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all.31369670687905722135421145230250775510205163037365421622926631851816084287298
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 8083879 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 8083879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
0.i2c_target_stress_all_with_rand_reset.24108705339099456522504233989005731548998170109537564126204627016659205289578
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11936942 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 11936942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_stress_all_with_rand_reset.111420843676224661228138227752771877555992591029666951113187646095288581379043
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 51892132 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 51892132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 49 failures:
1.i2c_target_stress_all_with_rand_reset.42389723023312901784429489473889069994877976507152321579113781509014661144799
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1908815735 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1908815735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.112891257769099482302012092346466794355060924340362367584245959963898741425595
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1099273513 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1099273513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
2.i2c_host_stress_all_with_rand_reset.38867996240483506922374136688869498346156206041519758480445941256345301784033
Line 5500, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5073027022 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5073027022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_stress_all_with_rand_reset.98651085857360402525254687203504538986036357675893043167776779008362337534784
Line 5691, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5160594572 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5160594572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:66) [i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == * (* [*] vs * [*]) has 29 failures:
3.i2c_host_stretch_timeout.2354380946320173789763289343019097010363363067574722806181170458985488718634
Line 366, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 61805211 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (30 [0x1e] vs 1 [0x1])
UVM_INFO @ 61805211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_host_stretch_timeout.103007754012324700056639393502183451538115520615470165146126237882273736947499
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 144124677 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (11 [0xb] vs 1 [0x1])
UVM_INFO @ 144124677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
3.i2c_host_stress_all.47508378337060603471337261531047403491289377723799844028567348736555142647399
Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 16117867 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (14 [0xe] vs 1 [0x1])
UVM_INFO @ 16117867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_host_stress_all.9669194057369516581855950543430714329054712707369722120221663201544523862145
Line 298, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 148602788 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (9 [0x9] vs 1 [0x1])
UVM_INFO @ 148602788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
5.i2c_host_stress_all_with_rand_reset.73180035977184188820727489577947937129840335458919445215570158642307771863143
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 59254336 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (63 [0x3f] vs 1 [0x1])
UVM_INFO @ 59254336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_host_stress_all_with_rand_reset.102543790961098773552226979542608899465114710831845913994143522739857950822288
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 75009103 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (11 [0xb] vs 1 [0x1])
UVM_INFO @ 75009103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:773) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 26 failures:
2.i2c_target_stress_all_with_rand_reset.45202271455217637980421957203731481571050127177824410423304893066989579564834
Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2940756158 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2940756158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_all_with_rand_reset.70539249758477003626311632423358046616907695109147977931570394230281294730861
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1736963711 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1736963711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
3.i2c_target_perf.102014184878133625686288920980224246746250203603930665273223640040709640660057
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_perf/latest/run.log
UVM_ERROR @ 38655684 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 38655684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_perf.44997821954794957319129230149120628041813030607414802443913912560643493665667
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_perf/latest/run.log
UVM_ERROR @ 22083424 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 22083424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
4.i2c_target_stress_all.61732357203273105359657096028215801665202320037750408244338696265476820882099
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 4277321065 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4277321065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all.66362009815602283496865960677531603490623956749132376843014600970308317126375
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 18947815 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 18947815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 4 failures:
6.i2c_target_stress_all_with_rand_reset.110775225603582701263954399162280364777159797785673922064125886939365072392441
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10157050407 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x2575fd94) == 0x0
UVM_INFO @ 10157050407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all_with_rand_reset.97668857392483595706403569756846821407963278845499579927470293054504903094697
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 33582534167 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x3b80e414) == 0x0
UVM_INFO @ 33582534167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred! has 3 failures:
Test i2c_target_unexp_stop has 2 failures.
21.i2c_target_unexp_stop.14914297852275938684146734544747336513471537200816239630182616909174870824174
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 10220327581 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10220327581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.i2c_target_unexp_stop.26966780639331448013933620898943219605827208464838537116390081837214160712440
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 10454502411 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10454502411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
38.i2c_target_stress_all.19326451354705433191460397981987791375014404575652285753676169737623392836366
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 12101080442 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 12101080442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_glitch_vseq.sv:197) virtual_sequencer [i2c_glitch_vseq] timed out waiting for state: StretchAddr has 2 failures:
0.i2c_target_glitch.14195535773969861048633577123717288133427621596916557649883259013054664701586
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 671578788 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
UVM_INFO @ 671578788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_glitch.56556271720923736565743587524536219392831974163385104708681591502292199819866
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log
UVM_ERROR @ 4730590947 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
UVM_INFO @ 4730590947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 2 failures:
4.i2c_target_stress_all_with_rand_reset.79137946534013985441281544682562686864798526600979803456610079640678918780177
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1783904881 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1783904881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.i2c_target_stress_all_with_rand_reset.9980807538517128295457260816323913295190562586128801192188293302671928318620
Line 318, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 12809700361 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 12809700361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 2 failures:
Test i2c_host_stress_all has 1 failures.
6.i2c_host_stress_all.104888080741187894277779730950813278410711993148039861750073080943537263331213
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
Job ID: smart:463ab845-baad-49b4-ac43-3fff87ddcba1
Test i2c_host_stretch_timeout has 1 failures.
20.i2c_host_stretch_timeout.83925459351414297003138331686105913230106217993159175651717589859344704408160
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stretch_timeout/latest/run.log
Job ID: smart:48f4860c-647f-40e6-ae5b-bcf74bdd547d
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 2 failures:
27.i2c_target_stress_all.20931678593803384839417889559730987750446972673832243486936547948012103486775
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 5899107099 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (43 [0x2b] vs 39 [0x27])
UVM_INFO @ 5899107099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.i2c_target_stress_all.102145902572167787896859584887942524194108339565329152456800350397508357463279
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 5731391662 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (43 [0x2b] vs 42 [0x2a])
UVM_INFO @ 5731391662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:968) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop has 1 failures:
2.i2c_target_perf.107457473955245991042279984821901731578023472998462837700320345489781428566572
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
UVM_ERROR @ 324972050 ps: (i2c_base_vseq.sv:968) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 324972050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
18.i2c_host_stress_all_with_rand_reset.98638383219297812609484043134809593674868204988278107729785882199221736240360
Line 4241, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14184115822 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
UVM_INFO @ 14184115822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
38.i2c_host_stress_all_with_rand_reset.506381793479153630630902099709767597613333854250703732923454691993156699761
Line 625, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3798880665 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
UVM_FATAL (i2c_base_vseq.sv:1147) [stop_interrupt_handler] wait timeout occurred! has 1 failures:
46.i2c_target_intr_stress_wr.6125680042056176356523338641423421994089017879830604356613702801787249237571
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 12834322335 ps: (i2c_base_vseq.sv:1147) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 12834322335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
46.i2c_target_stress_all_with_rand_reset.32248738849450523858466105246690382680532870081919957086634851687704687817857
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1859022189 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1859022189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
46.i2c_host_mode_toggle.113626387116768966117412812638505419951853306631850735083386072337374639848654
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---