I2C Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.579m	10.858ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	52.020s	2.824ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.760s	222.321us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.770s	25.452us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.600s	3.055ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.700s	150.357us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.300s	49.742us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.770s	25.452us	20	20	100.00
		i2c_csr_aliasing	1.700s	150.357us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	2.070s	107.908us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	40.001m	27.751ms	17	50	34.00
V2	host_perf	i2c_host_perf	49.110m	71.329ms	45	50	90.00
V2	host_override	i2c_host_override	0.730s	27.683us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.757m	4.565ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.783m	2.004ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.340s	356.945us	50	50	100.00
		i2c_host_fifo_fmt_empty	23.420s	460.948us	50	50	100.00
		i2c_host_fifo_reset_rx	12.010s	790.191us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.172m	30.130ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.680s	1.066ms	0	50	0.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.790m	15.354ms	49	50	98.00
V2	target_error_intr	i2c_target_unexp_stop	6.270s	1.552ms	5	50	10.00
V2	target_glitch	i2c_target_glitch	4.220s	721.878us	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	37.120s	34.673ms	2	50	4.00
V2	target_perf	i2c_target_perf	1.020s	309.016us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.278m	2.463ms	50	50	100.00
		i2c_target_intr_smoke	7.760s	6.348ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.863m	10.041ms	50	50	100.00
		i2c_target_fifo_reset_tx	2.105m	10.048ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	23.310s	10.836ms	14	50	28.00
		i2c_target_stress_rd	1.278m	2.463ms	50	50	100.00
		i2c_target_intr_stress_wr	18.750s	7.437ms	19	50	38.00
V2	target_timeout	i2c_target_timeout	8.790s	3.165ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	49.784m	38.919ms	38	50	76.00
V2	bad_address	i2c_target_bad_addr	5.850s	5.282ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.340s	590.082us	50	50	100.00
V2	alert_test	i2c_alert_test	0.710s	29.731us	50	50	100.00
V2	intr_test	i2c_intr_test	0.740s	65.546us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.840s	229.519us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.840s	229.519us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.760s	222.321us	5	5	100.00
		i2c_csr_rw	0.770s	25.452us	20	20	100.00
		i2c_csr_aliasing	1.700s	150.357us	5	5	100.00
		i2c_same_csr_outstanding	1.280s	68.337us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.760s	222.321us	5	5	100.00
		i2c_csr_rw	0.770s	25.452us	20	20	100.00
		i2c_csr_aliasing	1.700s	150.357us	5	5	100.00
		i2c_same_csr_outstanding	1.280s	68.337us	19	20	95.00
V2		TOTAL			1078	1392	77.44
V2S	tl_intg_err	i2c_tl_intg_err	2.290s	472.725us	20	20	100.00
		i2c_sec_cm	1.030s	67.559us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.290s	472.725us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.683m	8.772ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.176m	11.797ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	25.250s	919.913us	50	50	100.00
		TOTAL			1308	1722	75.96

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	7	100.00
V2	31	30	18	58.06
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.01	97.51	91.32	97.65	45.51	94.97	98.23	90.86

Failure Buckets

Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))' has 91 failures:

Test i2c_target_stress_wr has 36 failures.

0.i2c_target_stress_wr.8449018738832492937511329985158128867060126420594692719738140472033010386168
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 1833765446 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 1833765446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_wr.1438652656474471405116628755889336631092632897632428860062303433491308300173
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 2147293928 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 2147293928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 34 more failures.

Test i2c_target_intr_stress_wr has 31 failures.

0.i2c_target_intr_stress_wr.77394961383502580266373145858587795366650690783694979414666682257707212829485
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 1225042350 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 1225042350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_intr_stress_wr.31271307797131224453639547365297659876096781509813528734424269811230450574722
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 3145990764 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 3145990764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 29 more failures.

Test i2c_target_stress_all has 14 failures.

1.i2c_target_stress_all.8298031882785035429858269043361920420925231337137738943210094403749345273157
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 2051992687 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 2051992687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all.89641925048276201738701677405429722788794270985237831638142053390194575793731
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 11756483116 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 11756483116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test i2c_target_stress_all_with_rand_reset has 10 failures.

2.i2c_target_stress_all_with_rand_reset.60138466514001892459753366375268152106371251593063281869171217347806544866504
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 5931612965 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 5931612965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.40402104299176704680780826275134448338132721902400248847576174933346379814093
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 3634206047 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 3634206047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 64 failures:

Test i2c_host_stretch_timeout has 35 failures.

0.i2c_host_stretch_timeout.48299875357646002863514694005148501344350890674708205753789030978796913405609
Line 306, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @ 296279208 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (126 [0x7e] vs 14 [0xe])
  UVM_INFO @ 296279208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stretch_timeout.19290574647592916573022992031394137784075601034176361546003236364738282064991
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @  27697878 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (43 [0x2b] vs 8 [0x8])
  UVM_INFO @  27697878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 33 more failures.

Test i2c_host_stress_all_with_rand_reset has 13 failures.

2.i2c_host_stress_all_with_rand_reset.24293522659514536116349950426544965341236845400480009285796021335431297831132
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  45265994 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (54 [0x36] vs 6 [0x6])
  UVM_INFO @  45265994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_host_stress_all_with_rand_reset.35684611906063076022135389903349287137430338914929725643601587064291166624964
Line 395, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  87432278 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (286 [0x11e] vs 33 [0x21])
  UVM_INFO @  87432278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Test i2c_host_stress_all has 16 failures.

3.i2c_host_stress_all.3854184607459130436099250812485504227394377899210650116330001921352538380727
Line 1080, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 497686180 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (225 [0xe1] vs 25 [0x19])
  UVM_INFO @ 497686180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_host_stress_all.16635781391841556090709638060206206873562757180635376266555300597899683251557
Line 286, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 308913839 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (4 [0x4] vs 5 [0x5])
  UVM_INFO @ 308913839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

UVM_ERROR (i2c_base_vseq.sv:977) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 63 failures:
- Test i2c_target_unexp_stop has 45 failures.
  - 0.i2c_target_unexp_stop.63022788694908241916094204622379319284727160345750113166807095999241902235855
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 801549236 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 801549236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.112066053553590858662652475801099631820798911539055412851627408634071373818177
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1038242444 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 1038242444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 43 more failures.
- Test i2c_target_stress_all has 18 failures.
  - 0.i2c_target_stress_all.27033527275700504745865993754162825591104389781181870073763263076651748251964
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 1493633693 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 1493633693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_stress_all.101215032771196435934254948221422448724660441692025710898255136971662918682527
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 3235055590 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 3235055590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 45 failures:
- Test i2c_target_perf has 33 failures.
  - 0.i2c_target_perf.19035863533924242725719161237152343984590553663725704656297755670226636993042
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  55342957 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  55342957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_perf.99773501072201311953230283119913868142116707420434229228508517145382034336898
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 180795048 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 180795048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
- Test i2c_target_stress_all has 9 failures.
  - 15.i2c_target_stress_all.91196678212192670692924192276940454316211521524999943985259951501262405750086
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 10377027324 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 10377027324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.i2c_target_stress_all.5504179889075579351121005822102427437340928486875620708374171144573733232183
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 4925195477 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 4925195477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 43.i2c_target_stress_all_with_rand_reset.53071578981731493959636344490049017091087433868677600073674152338408367168308
    Line 356, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14058468244 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 14058468244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.i2c_target_stress_all_with_rand_reset.36798035795233009119044322252697162508861459306000160067394747831796285466257
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  12902018 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  12902018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 42 failures:

Test i2c_target_stress_all_with_rand_reset has 14 failures.

4.i2c_target_stress_all_with_rand_reset.113236801918563430769648764211454508062936631048922614651639788620546833524950
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 410012249 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 410012249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_target_stress_all_with_rand_reset.12280326765605048189806022668021674954526780439668559191757111239946930128836
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8022851120 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8022851120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test i2c_host_stress_all_with_rand_reset has 28 failures.

6.i2c_host_stress_all_with_rand_reset.13258358141776816615961173783792353753393151749166250675592522040522826132615
Line 3629, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 47109586190 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 47109586190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_host_stress_all_with_rand_reset.96481812762575196984076758833878453501599091314739437506126174901423151157211
Line 1052, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2563320391 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2563320391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 26 more failures.

UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:66) [i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == * (* [*] vs * [*]) has 32 failures:

Test i2c_host_stress_all has 11 failures.

0.i2c_host_stress_all.46156877072944960869282447694965818349105772016538398298521682301888379742543
Line 2945, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 9086020044 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (4 [0x4] vs 1 [0x1])
  UVM_INFO @ 9086020044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_host_stress_all.70234631094310981181074690176193343991247722566614122678318079228904478879315
Line 5055, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 23371831476 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (16 [0x10] vs 1 [0x1])
  UVM_INFO @ 23371831476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test i2c_host_stress_all_with_rand_reset has 6 failures.

1.i2c_host_stress_all_with_rand_reset.114901857976802947888097698489979991951066472797908237233218880138940928811005
Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 100887141 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (13 [0xd] vs 1 [0x1])
  UVM_INFO @ 100887141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.i2c_host_stress_all_with_rand_reset.33903114212374314232565651363342973624096295060120783688500686101344330614396
Line 4038, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6450775595 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (36 [0x24] vs 1 [0x1])
  UVM_INFO @ 6450775595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test i2c_host_stretch_timeout has 15 failures.

3.i2c_host_stretch_timeout.94670769307785603274484021123006010055450828552219403904183425626557920283917
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @ 113122277 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (81 [0x51] vs 1 [0x1])
  UVM_INFO @ 113122277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.i2c_host_stretch_timeout.90468888876023573525229664338266255964894749952158308739034140753683212783295
Line 386, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @  72245321 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (27 [0x1b] vs 1 [0x1])
  UVM_INFO @  72245321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

UVM_ERROR (i2c_scoreboard.sv:773) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 31 failures:
- Test i2c_target_perf has 15 failures.
  - 1.i2c_target_perf.233650391422768386162135063519921729489488547975659108139502817727427363135
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 171811485 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 171811485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_perf.109484443816059252566811776482830196837824600393202199380407792909005653680510
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  17186381 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  17186381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
- Test i2c_target_stress_all_with_rand_reset has 11 failures.
  - 3.i2c_target_stress_all_with_rand_reset.106746605544790274187502957323883847323477612806407701678477294298716687508964
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 214077138 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 214077138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.i2c_target_stress_all_with_rand_reset.49075534995373690295404455124784897754952672902083143976741513239730880351164
    Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5686952379 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5686952379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
- Test i2c_target_stress_all has 5 failures.
  - 7.i2c_target_stress_all.49583071821845172626763455111487123970899668914613529550039460204320747355475
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  35128573 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  35128573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.i2c_target_stress_all.89440848989654457752492403991013904618840566385299484825762559950558444036775
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 660784069 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 660784069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test i2c_host_stress_all_with_rand_reset has 2 failures.
  - 0.i2c_host_stress_all_with_rand_reset.102353871460739879940462647239764821400353094930785965851380281393740788617123
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:de4c7ab8-0b57-4537-9193-a15e8e80f345
```
  - 42.i2c_host_stress_all_with_rand_reset.56045087412058201242351262311635861070393943194767235557187566638318676230956
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:af843ccd-130c-41f9-ab68-0b9b17f1ccf0
```
- Test i2c_host_perf has 4 failures.
  - 2.i2c_host_perf.37434909898981244795133911363683801213698539760786871192097253675148760181835
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf/latest/run.log
```
  Job ID: smart:5442da69-3b58-45d5-8f3c-f84eec494ff3
```
  - 10.i2c_host_perf.3458767545295419779035164647654813998999995848507554669080270711787715513646
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_perf/latest/run.log
```
  Job ID: smart:08a446c1-5eb3-4879-8865-ac69d437018f
```
  - ... and 2 more failures.
- Test i2c_target_stretch has 12 failures.
  - 4.i2c_target_stretch.61969278609148388426557114293228808921318483783033233559501750184276511150165
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
```
  Job ID: smart:05cc9c42-aaf9-4ca8-b6fe-5056e7f97031
```
  - 5.i2c_target_stretch.104406331089591068920584792486066299366418860679545847452052658381349013851162
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
```
  Job ID: smart:0fe170b5-bc0f-42d1-becf-98ccef76d387
```
  - ... and 10 more failures.
- Test i2c_host_stress_all has 5 failures.
  - 7.i2c_host_stress_all.104299200374421805576628537067045890533442319152780166893563322858484968581747
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:e572806d-fab2-4c1c-8884-fcbace81b494
```
  - 22.i2c_host_stress_all.74716488775048751352291854644507429662449934431229475494859643781816296346028
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:cabc44af-254b-42a4-98ee-24516e94d99f
```
  - ... and 3 more failures.
- Test i2c_host_mode_toggle has 1 failures.
  - 14.i2c_host_mode_toggle.43406483642718248953273026422197870738651670358573615666920313842704521304068
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log
```
  Job ID: smart:363533b1-6154-4f46-a07a-72b8439b9acc
```
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
- Test i2c_target_stress_all_with_rand_reset has 6 failures.
  - 0.i2c_target_stress_all_with_rand_reset.45031469370658337198147762736956720202332556548334709679010483092594344934346
    Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 126750303 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 126750303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 13.i2c_target_stress_all_with_rand_reset.93117895757575443509230816787540537734329623158990114040263672515460298166506
    Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 122654390 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 122654390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 1.i2c_target_stress_all_with_rand_reset.9884248225101585712539721283614566432059517795465503065520448954908316010160
    Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11797115814 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x295e6594) == 0x0
  UVM_INFO @ 11797115814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.i2c_target_stress_all_with_rand_reset.65721719393273722648187546563914728760938516025841451738823265827890105059618
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10086474712 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xa89f4d94) == 0x0
  UVM_INFO @ 10086474712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred! has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 10.i2c_target_stress_all_with_rand_reset.70546464022544022873194228736613131349136880241669654794118324345772128308851
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10791667397 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10791667397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.i2c_target_stress_all_with_rand_reset.98132191065770127667157401728094193481381106356665136256096114797146156108503
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11720312284 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 11720312284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all has 1 failures.
  - 36.i2c_target_stress_all.17632146696556610132784254304959066705826662717916121940821574428856858954877
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 11686440791 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 11686440791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_glitch_vseq.sv:197) virtual_sequencer [i2c_glitch_vseq] timed out waiting for state: StretchAddr has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.109360342852762414145717252035401181260765520183107593798381552115139587766313
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 3059689285 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
  UVM_INFO @ 3059689285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.11394160618448929174015990693806673899885284704859123800823057563639601545763
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 721878376 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
  UVM_INFO @ 721878376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_base_vseq.sv:977) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop has 2 failures:
- Test i2c_target_perf has 2 failures.
  - 6.i2c_target_perf.15273368421045703078568190172480566636328731702948035569166373827080304372424
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  30689564 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
  UVM_INFO @  30689564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.i2c_target_perf.104009260505198455141972320370068978178913404916614558831336773277946271506030
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 186148590 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
  UVM_INFO @ 186148590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 0.i2c_same_csr_outstanding.29310791734313941870500857750063881579866048337890218065501573771502281476911
    Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  14216474 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  14216474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 8.i2c_host_stress_all_with_rand_reset.8263385454591707386086738215452443118674788304991437947718021202696735831058
    Line 6372, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34662439366 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (8 [0x8] vs 3 [0x3])
  UVM_INFO @ 34662439366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 27.i2c_host_perf.68939793158730028469023084334479214789402272836278505691576602058421251809830
    Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_perf/latest/run.log
```
  UVM_ERROR @ 268077575 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 27.i2c_target_stress_all.43507728754743694698610127857488587708507523365086592990232033225532602350199
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 20581314596 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (10 [0xa] vs 4 [0x4])
  UVM_INFO @ 20581314596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_perf_vseq.sv:206) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 48.i2c_host_stress_all.29109287618928510981431424772563267644315879758726477209891157188007062998950
    Line 6361, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 82505845439 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
  UVM_INFO @ 82505845439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```