919341eb22| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.706m | 4.077ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 56.710s | 2.724ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.740s | 40.444us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.780s | 40.235us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.500s | 2.702ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.670s | 38.507us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.620s | 121.096us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.780s | 40.235us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.670s | 38.507us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 154 | 155 | 99.35 | |||
| V2 | host_error_intr | i2c_host_error_intr | 1.960s | 103.147us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 57.371m | 41.521ms | 16 | 50 | 32.00 |
| V2 | host_maxperf | i2c_host_perf | 58.946m | 73.326ms | 45 | 50 | 90.00 |
| V2 | host_override | i2c_host_override | 0.780s | 88.013us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.804m | 5.895ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.695m | 26.642ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.320s | 545.389us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 18.570s | 1.411ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 10.520s | 197.976us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.559m | 10.379ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 6.590s | 125.069us | 0 | 50 | 0.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.585m | 1.763ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 6.920s | 3.904ms | 10 | 50 | 20.00 |
| V2 | target_glitch | i2c_target_glitch | 4.000s | 1.296ms | 0 | 2 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 3.885m | 15.397ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 1.230s | 442.503us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.041m | 5.832ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.460s | 6.174ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.838m | 10.093ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.849m | 10.175ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 36.690s | 18.621ms | 14 | 50 | 28.00 |
| i2c_target_stress_rd | 1.041m | 5.832ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 13.980s | 5.832ms | 17 | 50 | 34.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.280s | 3.085ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 56.663m | 44.634ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.730s | 1.269ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.340s | 2.487ms | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_host_fifo_watermark | 5.804m | 5.895ms | 50 | 50 | 100.00 |
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_txrst_on_cond | target_mode_txrst_on_cond | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.680s | 17.700us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.730s | 22.312us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.640s | 142.977us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.640s | 142.977us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.740s | 40.444us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.780s | 40.235us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.670s | 38.507us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.180s | 150.531us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.740s | 40.444us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.780s | 40.235us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.670s | 38.507us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.180s | 150.531us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1084 | 1392 | 77.87 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.150s | 153.924us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.970s | 67.890us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.150s | 153.924us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 15.726m | 7.994ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 2.731m | 10.427ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 23.590s | 595.062us | 50 | 50 | 100.00 | |
| TOTAL | 1313 | 1722 | 76.25 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 36 | 30 | 19 | 52.78 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.67 | 97.23 | 91.15 | 97.65 | 44.23 | 94.57 | 98.23 | 90.65 |
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))' has 92 failures:
0.i2c_target_stress_wr.36158515328733352374672719696262385353084011306920380062093014729307451265905
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 2200618263 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 2200618263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_wr.30731028308734609546592383897458264459601526319135097900186486861763116623610
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 2768072289 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 2768072289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
0.i2c_target_stress_all_with_rand_reset.60539069721591529211527673364230956944305751366165270000520158196278117675769
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 2418859846 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 2418859846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.22982669953412852452514480944703210070110868014308375607167257068826900212570
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 2715064907 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 2715064907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
1.i2c_target_intr_stress_wr.98082249083941595555735455174608799170200910995212216262762867386067369111156
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 1361995472 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 1361995472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_intr_stress_wr.49815240230410647080144413266177361350421757034682411382023312137695149341004
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 1129952478 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 1129952478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
2.i2c_target_stress_all.93281978730790888282830866351211415953262272067970742339578619740709269464936
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 1960662744 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 1960662744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all.102798187678812966214018674723871101517262522253275264652160117762986796071450
Line 290, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
UVM_ERROR @ 29273021288 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
UVM_INFO @ 29273021288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 58 failures:
0.i2c_host_stretch_timeout.88515248304026192693832363522143492026244558852674577789530202992189278996866
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 21506184 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (22 [0x16] vs 4 [0x4])
UVM_INFO @ 21506184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stretch_timeout.5963724960490635476104218898701257975852632301610424485433390405024650445917
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 169596774 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (5 [0x5] vs 4 [0x4])
UVM_INFO @ 169596774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
2.i2c_host_stress_all.72362488528455787207866253315111178601581230972228066901979691148984244309551
Line 993, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 9689460949 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (1 [0x1] vs 21 [0x15])
UVM_INFO @ 9689460949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_host_stress_all.9099469766509788939105489628992865231951510978356029715917448791243651148853
Line 6265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 7291444189 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (18 [0x12] vs 2 [0x2])
UVM_INFO @ 7291444189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
7.i2c_host_stress_all_with_rand_reset.17990235940827136626534297089345706764796053559142608758805349668743065948346
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20652265 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (8 [0x8] vs 2 [0x2])
UVM_INFO @ 20652265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.i2c_host_stress_all_with_rand_reset.51752568719001903206085150570038102607871437874351867409615788807258521448588
Line 304, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 138508696 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (18 [0x12] vs 2 [0x2])
UVM_INFO @ 138508696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_base_vseq.sv:977) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 55 failures:
0.i2c_target_stress_all.13453320165844318481354714228441274323905094422953540171323680802451855803371
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 32882034553 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 32882034553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.68702926573544803587286644788175805817464171187095776808941519450799808618531
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1029441959 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1029441959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
2.i2c_target_unexp_stop.54109973948450951577299106578122493642533582668108285371927288997604089117545
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 759005785 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 759005785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.75176859748329082014789784116405310382080298496041905703072387769610418143288
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1631509835 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1631509835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 38 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 46 failures:
0.i2c_host_stress_all_with_rand_reset.55244425955649954101076711622400050431765406844484168497627107607793357889166
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4713647804 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4713647804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.53322349414197539052140905813603542314819694073033752575488214867196860072139
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 955099586 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 955099586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
4.i2c_target_stress_all_with_rand_reset.57935928127021520428215176219253026877642875900973486621270514758049672179980
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 884621476 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 884621476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all_with_rand_reset.77510234038139176311554097315555026350302528378779158410118706014168541277349
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8059891372 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8059891372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 44 failures:
0.i2c_target_perf.31291259454559915146357957106537041970765940877998914257891292567722545525431
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 9967814 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 9967814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.114555910518216561436527037963304600495943014025204985185840434788866086103018
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 150716000 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 150716000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
4.i2c_target_stress_all.24899469808833431217494353525210789194704523927368385637494796519116643638970
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 8832714892 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 8832714892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all.37831955528380171127563952252345567916840765093264066974689747112233576640503
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 4093876367 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 4093876367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
6.i2c_target_stress_all_with_rand_reset.29389147953519117729107384098524076931377138179599973404485789645501678688291
Line 316, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12217500483 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 12217500483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:66) [i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == * (* [*] vs * [*]) has 41 failures:
1.i2c_host_stress_all_with_rand_reset.105874351859001904468389952083447746928453086631612376390574755921385512442119
Line 1626, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7994221950 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (18 [0x12] vs 1 [0x1])
UVM_INFO @ 7994221950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_host_stress_all_with_rand_reset.59399598589943523854124285020549116630378455560114617602257864701195582689888
Line 392, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 86083079 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (21 [0x15] vs 1 [0x1])
UVM_INFO @ 86083079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
2.i2c_host_stretch_timeout.70968744272777478769169867365976330757411641255935079472933278900939927618549
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 23393942 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (12 [0xc] vs 1 [0x1])
UVM_INFO @ 23393942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_stretch_timeout.87357685478821272518037989957339242398757921886395046933940576253525694917495
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest/run.log
UVM_ERROR @ 318500354 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (201 [0xc9] vs 1 [0x1])
UVM_INFO @ 318500354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
3.i2c_host_stress_all.29324144179486911217306182740581611587560038889648895126592803827762034346608
Line 9408, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 20430468853 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (153 [0x99] vs 1 [0x1])
UVM_INFO @ 20430468853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_host_stress_all.81752093801168271160482768712537911672838111575656292768276718827194586168416
Line 1418, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 6515555506 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6515555506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (i2c_scoreboard.sv:773) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 35 failures:
5.i2c_target_stress_all_with_rand_reset.93618036981001919650724038028460755797309993388583351016392341499204861810026
Line 285, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8477729771 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 8477729771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.6658284748102365505285091982595154057716154461414334663537431596756537652280
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9451456 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 9451456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
7.i2c_target_stress_all.86022039537257344892377738708365754456464294198955650868720907677601685857039
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 3955857784 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3955857784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_all.111933048148491217435100223205859920831228798034760357859871024347496567947903
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1446920138 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1446920138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
14.i2c_target_perf.33104145572002924666102345628241402398715989536926319316053836638862907314955
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_perf/latest/run.log
UVM_ERROR @ 202914340 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 202914340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_perf.54408765932521589370024287717659623554948326945770363888693727318355617135129
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_perf/latest/run.log
UVM_ERROR @ 111561582 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 111561582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
Test i2c_target_stretch has 7 failures.
0.i2c_target_stretch.30955206926890181620110883368268585955727304259419597024714266031656533330658
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
Job ID: smart:2c93e7ea-72f4-4396-8fa5-88fd96c50f3f
3.i2c_target_stretch.51844084812955390534036206098353555973126696825762853126333274836661233291877
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
Job ID: smart:992d2b9a-0208-46e5-b74c-2ef1f9ae69ca
... and 5 more failures.
Test i2c_host_stress_all has 1 failures.
1.i2c_host_stress_all.90793508561763610635469582917069611499591502128851577026636007602124658383313
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:fddccf45-ea51-44ae-8fdd-be4ce5d9392b
Test i2c_host_perf has 4 failures.
11.i2c_host_perf.112681706366211654101075832937746851040882876069633678645671213017284891070717
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_perf/latest/run.log
Job ID: smart:15b81d53-fa84-4e19-9148-df554f497bb6
17.i2c_host_perf.50440100702793093973721077774089486585557148053627377490266085359462108440939
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_perf/latest/run.log
Job ID: smart:e40063fc-0967-4fda-a348-6019ebc2881e
... and 2 more failures.
Test i2c_host_stress_all_with_rand_reset has 1 failures.
48.i2c_host_stress_all_with_rand_reset.82635061051365947129835440499143447266800097902435245188027739517305994868857
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:5c4819ba-a7e2-4d89-ad08-248d644aaf7f
UVM_ERROR (i2c_base_vseq.sv:977) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop has 7 failures:
1.i2c_target_stress_all.106112577513620651769065802172107504545225875272095276400899323852242489518254
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 151909340 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 151909340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.i2c_target_stress_all.71000438624430627056700858796624992363396049930184622293883953309640643104543
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 10095521 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 10095521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
2.i2c_target_perf.66728039431612461403440714468179637530671639313209873669034390041049262377035
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
UVM_ERROR @ 10306162 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 10306162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_perf.111747091078103087553128988494730729515451329851662826780607706606153091838086
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_perf/latest/run.log
UVM_ERROR @ 52748287 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
UVM_INFO @ 52748287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 4 failures:
10.i2c_target_stress_all_with_rand_reset.96040703909047935046506323101119691305220096572883906743192225007344077528482
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10954299078 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x1cbfdc94) == 0x0
UVM_INFO @ 10954299078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all_with_rand_reset.87486127059591530918052766422566118017751447294947365046179705278360394897485
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10427059500 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xc99cc994) == 0x0
UVM_INFO @ 10427059500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
2.i2c_target_stress_all_with_rand_reset.95626339039922885814058511383499975270668075703662369840142983601055198335368
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2554260827 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2554260827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_stress_all_with_rand_reset.100151108280988025398259222918168489980438448050780655830821525149325167765408
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 50597239218 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 50597239218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_csr_bit_bash has 1 failures.
4.i2c_csr_bit_bash.14171081433016153463237637424635259599152283353377960177115784894438715820423
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 150154080 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 150154080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 3 failures:
Test i2c_target_stress_all has 2 failures.
30.i2c_target_stress_all.50624867450637907857543906545313710269071524199625035707130274041605621569923
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 13318659921 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (10 [0xa] vs 7 [0x7])
UVM_INFO @ 13318659921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.i2c_target_stress_all.107429351643990837338318785557592207187417810471440854151531908439033893707519
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 28050142156 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (10 [0xa] vs 7 [0x7])
UVM_INFO @ 28050142156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
31.i2c_target_stress_all_with_rand_reset.63201354684680486986729971167339014269182674237336565557516639659314441997347
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9355100083 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 12 [0xc])
UVM_INFO @ 9355100083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_glitch_vseq.sv:197) virtual_sequencer [i2c_glitch_vseq] timed out waiting for state: StretchAddr has 2 failures:
0.i2c_target_glitch.31543100395671233213044058854314084008886040998036050067824484924470302652250
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 1296318471 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
UVM_INFO @ 1296318471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_glitch.67715433093863636227561581554501487282066213593215287122957220270789941058798
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log
UVM_ERROR @ 1329962757 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
UVM_INFO @ 1329962757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
1.i2c_host_perf.23157147789921116757847707823342310925372089073479450807858905248361092898606
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_perf/latest/run.log
UVM_ERROR @ 21064626936 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
UVM_FATAL (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred! has 1 failures:
1.i2c_target_stress_all_with_rand_reset.114931174583607915937428962381894155188727692465632344614308257489361557446320
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14966029591 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 14966029591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
10.i2c_same_csr_outstanding.55130142536027921434290565759195276883070382659131212843238539217001886166868
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 25414675 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 25414675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_perf_vseq.sv:206) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 1 failures:
13.i2c_host_stress_all.22149451115786018046538631912322409704637612578087967471621908082720741782939
Line 4242, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 72414322419 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
UVM_INFO @ 72414322419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
27.i2c_host_stress_all_with_rand_reset.100079077358449357262153451575242856367808414788675237612929369985448937884070
Line 1460, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8086731277 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (6 [0x6] vs 3 [0x3])
UVM_INFO @ 8086731277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
46.i2c_host_stress_all_with_rand_reset.45253326954854594551990374994214199987209275349358795614195226403903742113960
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12137158 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 12137158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---