I2C Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.604m	4.087ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	49.150s	2.639ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.720s	28.226us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.770s	27.020us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.480s	1.888ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.800s	166.426us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.380s	106.778us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.770s	27.020us	20	20	100.00
		i2c_csr_aliasing	1.800s	166.426us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	2.010s	200.681us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	51.109m	76.367ms	21	50	42.00
V2	host_maxperf	i2c_host_perf	58.230m	25.509ms	44	50	88.00
V2	host_override	i2c_host_override	0.750s	66.318us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.207m	4.125ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.708m	8.148ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.250s	153.743us	50	50	100.00
		i2c_host_fifo_fmt_empty	24.590s	2.170ms	50	50	100.00
		i2c_host_fifo_reset_rx	10.540s	190.498us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.163m	9.833ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	5.300s	439.460us	0	50	0.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.654m	2.069ms	48	50	96.00
V2	target_error_intr	i2c_target_unexp_stop	7.940s	4.966ms	11	50	22.00
V2	target_glitch	i2c_target_glitch	3.360s	2.150ms	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	39.950s	34.770ms	2	50	4.00
V2	target_maxperf	i2c_target_perf	1.050s	162.211us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.212m	20.700ms	50	50	100.00
		i2c_target_intr_smoke	7.820s	1.296ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.718m	10.090ms	50	50	100.00
		i2c_target_fifo_reset_tx	2.311m	10.123ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	49.210s	21.016ms	14	50	28.00
		i2c_target_stress_rd	1.212m	20.700ms	50	50	100.00
		i2c_target_intr_stress_wr	10.350s	4.787ms	15	50	30.00
V2	target_timeout	i2c_target_timeout	7.990s	1.533ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	54.595m	39.653ms	45	50	90.00
V2	bad_address	i2c_target_bad_addr	5.460s	1.102ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.320s	599.201us	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	5.207m	4.125ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_txrst_on_cond	target_mode_txrst_on_cond			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.680s	23.053us	50	50	100.00
V2	intr_test	i2c_intr_test	0.690s	58.965us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.960s	491.082us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.960s	491.082us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.720s	28.226us	5	5	100.00
		i2c_csr_rw	0.770s	27.020us	20	20	100.00
		i2c_csr_aliasing	1.800s	166.426us	5	5	100.00
		i2c_same_csr_outstanding	1.150s	52.833us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.720s	28.226us	5	5	100.00
		i2c_csr_rw	0.770s	27.020us	20	20	100.00
		i2c_csr_aliasing	1.800s	166.426us	5	5	100.00
		i2c_same_csr_outstanding	1.150s	52.833us	19	20	95.00
V2		TOTAL			1089	1392	78.23
V2S	tl_intg_err	i2c_tl_intg_err	2.190s	1.135ms	19	20	95.00
		i2c_sec_cm	0.950s	67.234us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.190s	1.135ms	19	20	95.00
V2S		TOTAL			24	25	96.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	12.185m	14.098ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.949m	100.082ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	21.880s	1.971ms	50	50	100.00
		TOTAL			1318	1722	76.54

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	7	100.00
V2	36	30	18	50.00
V2S	2	2	1	50.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.32	97.79	91.54	97.65	46.79	95.29	98.23	90.97

Failure Buckets

Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))' has 98 failures:

Test i2c_target_intr_stress_wr has 35 failures.

0.i2c_target_intr_stress_wr.105222527633081738515526414030229781035458385007762249006079502555998876735142
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 583859864 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 583859864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_intr_stress_wr.101421806695029250006540295993056947063316081204103999653165072459219986175466
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 611187563 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 611187563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 33 more failures.

Test i2c_target_stress_wr has 36 failures.

1.i2c_target_stress_wr.59668838145916977418544737796684907009702479728724498930604535546323186965747
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 760689300 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 760689300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_wr.83047123802329409653187180945818722676489395823483733609158311658619440752023
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 1954965593 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 1954965593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 34 more failures.

Test i2c_target_stress_all has 12 failures.

4.i2c_target_stress_all.85876579608579125791419889324798256686000957061263600987633285686932999141355
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 3804440783 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 3804440783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.i2c_target_stress_all.28801563193993411979550542252532456057071456316639525620939131318542344376953
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 876967067 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 876967067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test i2c_target_stress_all_with_rand_reset has 15 failures.

4.i2c_target_stress_all_with_rand_reset.75017455386546117019437665005681078983891339162520874189856664996123847051814
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 5261640177 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 5261640177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.46805701344154407721068342856985923981583590724088486105037307588967092825801
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 2719235425 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 2719235425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 55 failures:
- Test i2c_target_stress_all has 15 failures.
  - 1.i2c_target_stress_all.3088786942827406057637467802028628303378136567500707737651937887234936427418
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  17925606 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  17925606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stress_all.24254805589869225488774238479652018720373055434749547350212262683940645406085
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  32268892 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  32268892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
- Test i2c_target_perf has 34 failures.
  - 2.i2c_target_perf.54915610689514520656647651421099824390765490340726482064514430922659942828663
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 200106760 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 200106760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.i2c_target_perf.108331543677211379456982992369128117148794194502642831156179380122486711385458
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 302043763 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 302043763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
- Test i2c_target_stress_all_with_rand_reset has 6 failures.
  - 14.i2c_target_stress_all_with_rand_reset.15092861770915416587175735026502773475639672887894942490464320643184687553240
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  11471289 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  11471289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.i2c_target_stress_all_with_rand_reset.109648767614801923178593579427951445993745840903178235576169948883893380206046
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 729571383 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 729571383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 52 failures:

Test i2c_host_stretch_timeout has 29 failures.

0.i2c_host_stretch_timeout.45281123486718112263767793793156089587401929496789160052494613024195259662985
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @  19303334 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (17 [0x11] vs 3 [0x3])
  UVM_INFO @  19303334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_host_stretch_timeout.72898075455610964187385217778688309774318396318320501651420500967208623020512
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @ 179723748 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (45 [0x2d] vs 5 [0x5])
  UVM_INFO @ 179723748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 27 more failures.

Test i2c_host_stress_all_with_rand_reset has 10 failures.

6.i2c_host_stress_all_with_rand_reset.8637197344081037900191271075147814106689352143035068520505955905411792776514
Line 7640, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 29008453239 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (12 [0xc] vs 2 [0x2])
  UVM_INFO @ 29008453239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.i2c_host_stress_all_with_rand_reset.9698320449600423937204158220924912708032109031292242472222278827718572345288
Line 387, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2362048909 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (31 [0x1f] vs 6 [0x6])
  UVM_INFO @ 2362048909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_host_stress_all has 13 failures.

8.i2c_host_stress_all.43945613163633695489081405484857070685958907974904170036048019853918641664783
Line 2295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 19958233985 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (18 [0x12] vs 2 [0x2])
  UVM_INFO @ 19958233985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.i2c_host_stress_all.64512138988401535105581654249817790927832180694055530717118064363009132737623
Line 404, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 5688739377 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (18 [0x12] vs 3 [0x3])
  UVM_INFO @ 5688739377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_ERROR (i2c_base_vseq.sv:977) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 51 failures:
- Test i2c_target_unexp_stop has 39 failures.
  - 0.i2c_target_unexp_stop.101000552996834017216975043631856340051271882956697203443262876190076902133221
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1605937992 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 1605937992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.106377058837605909277906022411283011143549396892458402994502561333957190840601
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 3924394252 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 3924394252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 37 more failures.
- Test i2c_target_stress_all has 12 failures.
  - 0.i2c_target_stress_all.105719015010575361581404403456311193608905574474389271584999556142723015552150
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 3923408836 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 3923408836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.i2c_target_stress_all.5409256257963776071240811025953531802634241313361023268706757380288146154035
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 985740886 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 985740886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 42 failures:

Test i2c_host_stress_all_with_rand_reset has 31 failures.

0.i2c_host_stress_all_with_rand_reset.37639653388833267496379928571197089465473026816003028515747843597558003356112
Line 6672, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5918095378 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5918095378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stress_all_with_rand_reset.11808388012647404794875976982913059278555252491015980171475270523277987997403
Line 1042, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 84085298703 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 84085298703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 29 more failures.

Test i2c_target_stress_all_with_rand_reset has 11 failures.

1.i2c_target_stress_all_with_rand_reset.71965225440722045810449277706302549832984400849155140913044485994433009782522
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 817759505 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 817759505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.34596543368216460487746516185276554565851106521351748242959615772810873838450
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8922359866 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8922359866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:66) [i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == * (* [*] vs * [*]) has 41 failures:

Test i2c_host_stretch_timeout has 21 failures.

1.i2c_host_stretch_timeout.93115617804230128613747517759354461126222398883490335818427449868013071271910
Line 310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @ 380931926 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (62 [0x3e] vs 1 [0x1])
  UVM_INFO @ 380931926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stretch_timeout.104950021705449803660034650197447156448009391344163944147886371086562131116555
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @  17282033 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (18 [0x12] vs 1 [0x1])
  UVM_INFO @  17282033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 19 more failures.

Test i2c_host_stress_all_with_rand_reset has 7 failures.

1.i2c_host_stress_all_with_rand_reset.25996712540264199704212014023588402279253528876855518545308288042347543297933
Line 2427, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2943398324 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (8 [0x8] vs 1 [0x1])
  UVM_INFO @ 2943398324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_host_stress_all_with_rand_reset.75679435511426273551474298554674641017571895939309130762140126178490675739452
Line 392, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1086182537 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 1086182537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test i2c_host_stress_all has 13 failures.

3.i2c_host_stress_all.36525363180397476763723155222383109178669391716904467537906096485228534899246
Line 3373, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 56562196318 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (17 [0x11] vs 1 [0x1])
  UVM_INFO @ 56562196318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_host_stress_all.51108611120576708246118275730961788315110638380744078729355481733516204617795
Line 4636, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 4764260353 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (45 [0x2d] vs 1 [0x1])
  UVM_INFO @ 4764260353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_ERROR (i2c_scoreboard.sv:773) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 25 failures:
- Test i2c_target_perf has 15 failures.
  - 0.i2c_target_perf.1697840922216133916439237174189427538261455134178808837184850003739415033051
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 127695737 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 127695737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.36617979627866245316950942164966454044527634515530755051981922606850211626680
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  15641952 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  15641952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
- Test i2c_target_stress_all_with_rand_reset has 7 failures.
  - 0.i2c_target_stress_all_with_rand_reset.90989558390345294966366920929907730015890914670340785822182924091564334897706
    Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1445601657 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1445601657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_stress_all_with_rand_reset.106108432441123826881247517642905889459077314191633065600555945523011259922923
    Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4522308325 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4522308325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
- Test i2c_target_stress_all has 3 failures.
  - 11.i2c_target_stress_all.60288377009048698490833905949453154180931309651021606597550351513443387744488
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  30161156 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  30161156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.i2c_target_stress_all.97402544722986173790189568659458470369905164923507680456499623464463747788116
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 5366776125 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5366776125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test i2c_host_stress_all has 1 failures.
  - 0.i2c_host_stress_all.89828784248764266599937186962757764367812787354066423775592332148219885062402
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:886d66fb-c2c4-440b-8dd6-b44205567469
```
- Test i2c_host_perf has 5 failures.
  - 3.i2c_host_perf.95103060031737135815454043476989169349598092489355096201552930427456134008932
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_perf/latest/run.log
```
  Job ID: smart:678b937b-5683-4942-884a-416a87ce4896
```
  - 5.i2c_host_perf.97816043263440973909039594195743205959806615726080252414654440464968172064087
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_perf/latest/run.log
```
  Job ID: smart:b12f3de8-2ac7-446d-87c1-85b715cf934f
```
  - ... and 3 more failures.
- Test i2c_target_stretch has 5 failures.
  - 3.i2c_target_stretch.52865655680915206814013857610042596872144985531805911222236570953496001592396
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
```
  Job ID: smart:eb76bbc4-a21e-42db-b29e-1e63d6c6b1a2
```
  - 6.i2c_target_stretch.42422459055531005773504061843551522959770441887764334584689559483540780366750
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
```
  Job ID: smart:d042ff71-2921-4e0b-9cc0-fd220d9c34f9
```
  - ... and 3 more failures.
- Test i2c_host_mode_toggle has 2 failures.
  - 23.i2c_host_mode_toggle.1028252900912604271445226810251678438707994888926988216324782930085234107791
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log
```
  Job ID: smart:f84c9d10-237f-4249-8145-467ed2f58ad4
```
  - 35.i2c_host_mode_toggle.61397429513092058249364219096500242676693160539261729537995915487933801903153
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_mode_toggle/latest/run.log
```
  Job ID: smart:af1c4690-fd19-49c7-98f4-a76406fc8788
```
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 31.i2c_host_stress_all_with_rand_reset.38808128097600825796707084977089079871470416208332491084764680762944449036224
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b22138a0-f1bb-4d3f-bfce-5e513b27ca98
```
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 5 failures:
- Test i2c_target_stress_all has 4 failures.
  - 7.i2c_target_stress_all.16059664582201409308984287889555977120436944069535615682882250845304379164166
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 931687103 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (17 [0x11] vs 16 [0x10])
  UVM_INFO @ 931687103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.i2c_target_stress_all.23870028699887442952746746242975792436153501973184448141618905581289388088321
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 2038911586 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 2038911586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 22.i2c_target_stress_all_with_rand_reset.8366670223189296423494414996941480620480329845424109072175764368446961032344
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3026600800 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 3 [0x3])
  UVM_INFO @ 3026600800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:
- Test i2c_target_stress_all_with_rand_reset has 5 failures.
  - 9.i2c_target_stress_all_with_rand_reset.11953852767635346207905422029158960205713412035544012087651964684079214850174
    Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 680574944 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 680574944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 13.i2c_target_stress_all_with_rand_reset.62020545311857637574433275393101143852236810739752016799170066968358487368939
    Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 2441915704 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 2441915704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 4 failures.
  - 6.i2c_target_stress_all_with_rand_reset.9137678655394591901231270079342124726023509560686940513784081249391558414014
    Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10342284719 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x56764a94) == 0x0
  UVM_INFO @ 10342284719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.i2c_target_stress_all_with_rand_reset.27427323295676606774532193569667306214059916234491508553471884975584754225188
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12637633120 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xdd956294) == 0x0
  UVM_INFO @ 12637633120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (i2c_base_vseq.sv:977) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop has 3 failures:
- Test i2c_target_stress_all has 2 failures.
  - 10.i2c_target_stress_all.25775859825231141975561888795241704561084019331134250298649911550721508809531
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  25987632 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
  UVM_INFO @  25987632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.i2c_target_stress_all.102858936075610218862970387181687758768925237059742385041907954567788805120586
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  46880614 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
  UVM_INFO @  46880614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_perf has 1 failures.
  - 16.i2c_target_perf.106298236418919121040737973418369828756431060118263600561316337948453478233170
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  39686099 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
  UVM_INFO @  39686099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_glitch_vseq.sv:197) virtual_sequencer [i2c_glitch_vseq] timed out waiting for state: StretchAddr has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.69483985845455995595028098320316058666982133620733539455905594968515018896936
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 2149910717 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
  UVM_INFO @ 2149910717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.19515834581998031043984079507600974827296513747576845907159538321008716717689
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 923720675 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
  UVM_INFO @ 923720675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending 'scl_i' has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 0.i2c_host_perf.21708960079219216175274068139744161938086729818246697146997100864751389744646
    Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_perf/latest/run.log
```
      Offending 'scl_i'
  UVM_ERROR @ 613394460 ps: (i2c_fsm.sv:1677) [ASSERT FAILED] SclInputGlitch_A
  UVM_INFO @ 613394460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 0.i2c_same_csr_outstanding.39923806737855951557205858934125323155816009260013553603520259507324894679186
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 167424773 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @ 167424773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 1.i2c_host_stress_all.44329891422096475460105839680586695625341470206099124155297876966808754827390
    Line 673, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!((host_enable_i && (scl_d != scl_q)) && (sda_d != sda_q)))' has 1 failures:
- Test i2c_tl_intg_err has 1 failures.
  - 7.i2c_tl_intg_err.77804330885693475299654485631910383806842483810023336125090192066171398194251
    Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_tl_intg_err/latest/run.log
```
      Offending '(!((host_enable_i && (scl_d != scl_q)) && (sda_d != sda_q)))'
  UVM_ERROR @  64148169 ps: (i2c_fsm.sv:1689) [ASSERT FAILED] SclSdaChangeNotSimultaneous_A
  UVM_INFO @  64148169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job i2c-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 18.i2c_host_stress_all.81665973971409343517584083678346526620726476156464895163176154444167084316638
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:b687fa7e-d652-440d-8bf4-801f9d1e1525
```
UVM_FATAL (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 36.i2c_target_stress_all_with_rand_reset.1657300439079340747298359458430079294503199993099845746873593886413435328153
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10352535338 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10352535338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 39.i2c_host_stress_all_with_rand_reset.34287836319222478387433553270136826837493872072243869196717572565787869982539
    Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1465769238 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```