I2C Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.376m	3.182ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	49.750s	2.466ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.750s	48.069us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.810s	50.279us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.670s	504.523us	3	5	60.00
V1	csr_aliasing	i2c_csr_aliasing	1.840s	437.811us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.580s	60.961us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.810s	50.279us	20	20	100.00
		i2c_csr_aliasing	1.840s	437.811us	5	5	100.00
V1		TOTAL			153	155	98.71
V2	host_error_intr	i2c_host_error_intr	1.980s	103.140us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	59.637m	102.043ms	10	50	20.00
V2	host_maxperf	i2c_host_perf	49.974m	53.444ms	46	50	92.00
V2	host_override	i2c_host_override	0.740s	45.897us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.175m	10.274ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.911m	2.162ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.250s	571.861us	50	50	100.00
		i2c_host_fifo_fmt_empty	26.670s	516.452us	50	50	100.00
		i2c_host_fifo_reset_rx	11.650s	3.970ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.983m	4.232ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.920s	302.869us	0	50	0.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.754m	3.870ms	47	50	94.00
V2	target_error_intr	i2c_target_unexp_stop	7.080s	1.632ms	12	50	24.00
V2	target_glitch	i2c_target_glitch	3.950s	1.603ms	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	1.058m	17.863ms	1	50	2.00
V2	target_maxperf	i2c_target_perf	1.030s	301.903us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.128m	6.216ms	50	50	100.00
		i2c_target_intr_smoke	7.480s	1.304ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.637m	10.090ms	50	50	100.00
		i2c_target_fifo_reset_tx	2.090m	10.075ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	33.240s	15.216ms	10	50	20.00
		i2c_target_stress_rd	1.128m	6.216ms	50	50	100.00
		i2c_target_intr_stress_wr	14.510s	6.164ms	14	50	28.00
V2	target_timeout	i2c_target_timeout	8.380s	1.651ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	40.914m	32.658ms	41	50	82.00
V2	bad_address	i2c_target_bad_addr	5.140s	3.758ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.260s	582.551us	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	6.175m	10.274ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_txrst_on_cond	target_mode_txrst_on_cond			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.660s	16.535us	50	50	100.00
V2	intr_test	i2c_intr_test	0.780s	44.697us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.960s	447.967us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.960s	447.967us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.750s	48.069us	5	5	100.00
		i2c_csr_rw	0.810s	50.279us	20	20	100.00
		i2c_csr_aliasing	1.840s	437.811us	5	5	100.00
		i2c_same_csr_outstanding	1.200s	235.566us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.750s	48.069us	5	5	100.00
		i2c_csr_rw	0.810s	50.279us	20	20	100.00
		i2c_csr_aliasing	1.840s	437.811us	5	5	100.00
		i2c_same_csr_outstanding	1.200s	235.566us	20	20	100.00
V2		TOTAL			1071	1392	76.94
V2S	tl_intg_err	i2c_tl_intg_err	2.330s	146.970us	20	20	100.00
		i2c_sec_cm	0.930s	131.833us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.330s	146.970us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.594m	7.760ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	3.002m	10.225ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	22.020s	541.643us	50	50	100.00
		TOTAL			1299	1722	75.44

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	6	85.71
V2	36	30	19	52.78
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.01	97.51	91.32	97.65	45.51	94.97	98.23	90.86

Failure Buckets

Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))' has 96 failures:

Test i2c_target_stress_wr has 40 failures.

0.i2c_target_stress_wr.67594032662327204717069996276902803432536870898523481245154316845267805394382
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 4633591168 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 4633591168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_wr.21231182938298754427190556710987718124688910649468191216497141720017753865287
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 2777276053 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 2777276053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 38 more failures.

Test i2c_target_intr_stress_wr has 34 failures.

0.i2c_target_intr_stress_wr.58782570753350847908976904357602598828966612302396547417516470710702331968012
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 3283863347 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 3283863347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_intr_stress_wr.8474751934459837667448660561172111474310290610407821317604783301958901381319
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 558036901 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 558036901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 32 more failures.

Test i2c_target_stress_all has 15 failures.

1.i2c_target_stress_all.110464528172602014744193250962648537890036762299436810924893694495439620796983
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 1345239446 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 1345239446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_target_stress_all.20950285302215209754746930194399196729734658548536313480535869928409690161626
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 1283046709 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 1283046709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

1.i2c_target_stress_all_with_rand_reset.35689714653975205669387011807298399110118797797655637591444690688441091947567
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 1294257409 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 1294257409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.i2c_target_stress_all_with_rand_reset.108570113681919912834066104506560985865686555971580837966580907725170705484831
Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(acq_fifo_wvalid_i) && $stable(acq_fifo_wdata_i))'
  UVM_ERROR @ 5031859559 ps: (i2c_fifos.sv:312) [ASSERT FAILED] AcqWriteStableBeforeHandshake_A
  UVM_INFO @ 5031859559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 72 failures:

Test i2c_host_stretch_timeout has 31 failures.

0.i2c_host_stretch_timeout.49767512191612062933716282905175555649443142746318214025155289506678651059653
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @   5769746 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (18 [0x12] vs 2 [0x2])
  UVM_INFO @   5769746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stretch_timeout.18500275615083014034813263331610576823316361625698309483174039980434986433130
Line 326, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @  53648404 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (1 [0x1] vs 9 [0x9])
  UVM_INFO @  53648404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 29 more failures.

Test i2c_host_stress_all has 25 failures.

0.i2c_host_stress_all.105003966873663967142112541677637033052014159772752551423810096051346578913360
Line 426, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 120720193 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (24 [0x18] vs 6 [0x6])
  UVM_INFO @ 120720193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all.77142305711580694814100967927727330687275904191497524753794346556679271586842
Line 2056, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 12607598901 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (288 [0x120] vs 32 [0x20])
  UVM_INFO @ 12607598901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more failures.

Test i2c_host_stress_all_with_rand_reset has 16 failures.

3.i2c_host_stress_all_with_rand_reset.21281810057250212824395737753537209058442414043257734044782478665348251626923
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 104319673 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (7 [0x7] vs 3 [0x3])
  UVM_INFO @ 104319673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_host_stress_all_with_rand_reset.34252138272598561640660923690468183201114117596003714576049303522841505738247
Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 218752358 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (5 [0x5] vs 4 [0x4])
  UVM_INFO @ 218752358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

UVM_ERROR (i2c_base_vseq.sv:977) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 58 failures:

Test i2c_target_stress_all has 20 failures.

0.i2c_target_stress_all.88713868673169278256948309300536151004481362136065899275992973186193927400845
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 10156687987 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 10156687987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all.40823817763444316550457811084516358636331363017852907931149439998163201219140
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 2545445061 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 2545445061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Test i2c_target_unexp_stop has 38 failures.

2.i2c_target_unexp_stop.27252295213873984900298051156334663601514300912395277630034117569034564718454
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 3510805751 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 3510805751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_unexp_stop.84655139619870619419828280832871701927453115371757381207204362745229841937208
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 3274131479 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 3274131479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 36 more failures.

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 55 failures:
- Test i2c_target_stress_all_with_rand_reset has 11 failures.
  - 0.i2c_target_stress_all_with_rand_reset.40588733695323740933494397135673437268618223916568690817469175401317145055382
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109959085 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 109959085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_target_stress_all_with_rand_reset.108863906576821581390441668884205518281891332916804126993063219909572856804703
    Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 236865377 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 236865377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
- Test i2c_target_perf has 38 failures.
  - 1.i2c_target_perf.2928906289432357834336503753603867746191551880192827656489540030156491563944
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  16803034 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  16803034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_perf.99895258187216388966971966972077162365056744370638000014552802188152054698482
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  16578463 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  16578463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 36 more failures.
- Test i2c_target_stress_all has 6 failures.
  - 5.i2c_target_stress_all.48720999756030696419599395269554872875857183972713421436142059790922408172914
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  82542497 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  82542497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.i2c_target_stress_all.5852959251493357402137898762461155013456859325684140538875681090500185357207
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  61001041 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  61001041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:

Test i2c_host_stress_all_with_rand_reset has 28 failures.

0.i2c_host_stress_all_with_rand_reset.23067037527410939403079302682375138649422878140383098308634811932688063651500
Line 371, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7622425524 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7622425524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.103236841057490680605297809662251157683575683899726466164547633007157006179530
Line 283, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 665751521 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 665751521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 26 more failures.

Test i2c_target_stress_all_with_rand_reset has 11 failures.

5.i2c_target_stress_all_with_rand_reset.30035992352018378158778402308534135672094852280322642046512688776059726828856
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9546110441 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9546110441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.i2c_target_stress_all_with_rand_reset.96175524242822753044594858058777184578969884559226421461990493145419025864463
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2194001229 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2194001229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:66) [i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == * (* [*] vs * [*]) has 35 failures:

Test i2c_host_stretch_timeout has 18 failures.

1.i2c_host_stretch_timeout.74219127626750553632608801399318934291032849852247551513376981787591417928006
Line 386, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @  69605624 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (5 [0x5] vs 1 [0x1])
  UVM_INFO @  69605624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_host_stretch_timeout.66512747140602345436350476671570169737253584926263301622189329872242065647572
Line 414, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest/run.log

  UVM_ERROR @ 446910961 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (105 [0x69] vs 1 [0x1])
  UVM_INFO @ 446910961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 16 more failures.

Test i2c_host_stress_all_with_rand_reset has 6 failures.

4.i2c_host_stress_all_with_rand_reset.23020637300907940266733923940150910709278579065221343789515725948392164940811
Line 513, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3554883172 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (297 [0x129] vs 1 [0x1])
  UVM_INFO @ 3554883172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.i2c_host_stress_all_with_rand_reset.18182910271191760790965773878122005833767345341440718701820660899607752909291
Line 6415, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20850373340 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (13 [0xd] vs 1 [0x1])
  UVM_INFO @ 20850373340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test i2c_host_stress_all has 11 failures.

11.i2c_host_stress_all.81262325741932437420064454791359020958887465701306664066896987411656015525284
Line 9726, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 74963329329 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (111 [0x6f] vs 1 [0x1])
  UVM_INFO @ 74963329329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.i2c_host_stress_all.2581551750467934580184056451480914862629449285561756311261392310464228676112
Line 8908, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 6460411683 ps: (i2c_host_stretch_timeout_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_rd_stretch == 1 (8 [0x8] vs 1 [0x1])
  UVM_INFO @ 6460411683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (i2c_scoreboard.sv:773) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 31 failures:
- Test i2c_target_perf has 11 failures.
  - 0.i2c_target_perf.67270703574214705025090723814427437122090492960160097973275360546594028739495
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  62163210 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  62163210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.i2c_target_perf.40381690132757824513331142950758472867950789744677944649938842915131902058866
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  10784840 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  10784840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
- Test i2c_target_stress_all has 8 failures.
  - 3.i2c_target_stress_all.89287582209097211034595651553763393608752811189172028265881248748182753840805
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @  43233741 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  43233741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.i2c_target_stress_all.44123138338234959869821858848861457175947583713453072362247476767135643466943
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 147323064 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 147323064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
- Test i2c_target_stress_all_with_rand_reset has 10 failures.
  - 3.i2c_target_stress_all_with_rand_reset.73509136864732396330437830219586684931851983743822962187117628655655817746412
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  65971158 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  65971158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_stress_all_with_rand_reset.75589023661099201660964293904194511925278238940969122488816254796921098310345
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  65750530 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
  UVM_INFO @  65750530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
- Test i2c_target_intr_stress_wr has 2 failures.
  - 10.i2c_target_intr_stress_wr.71957439010184987205844172173784371231660389660990736905948045391946095423012
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_ERROR @ 10938981196 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 10938981196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.i2c_target_intr_stress_wr.6243740514848211137652833303565162796490129989155217929757377846317939779569
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_ERROR @ 14769738801 ps: (i2c_scoreboard.sv:773) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 14769738801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test i2c_target_stretch has 9 failures.
  - 2.i2c_target_stretch.58204543525119650950678910779776573756863775929966655424542605537475498320434
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
```
  Job ID: smart:e8a1b971-8261-4ede-8d3c-1ebbdbb29cb2
```
  - 4.i2c_target_stretch.58365316119854155028237707148637913184513440228288421517112913399292629699735
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
```
  Job ID: smart:cf9ce0a9-9caa-43f8-b01e-a3139fef6a22
```
  - ... and 7 more failures.
- Test i2c_host_perf has 4 failures.
  - 4.i2c_host_perf.104975333685728950026702952193417612370457656389136388623354972458344524351893
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_perf/latest/run.log
```
  Job ID: smart:08616913-f8ce-43c4-aa0d-c1fc031fad57
```
  - 12.i2c_host_perf.48861245307866741140185518582248903144333468106419114019562516774281295483287
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_perf/latest/run.log
```
  Job ID: smart:4b406652-3c2e-4a3e-8ef6-e018617b7b38
```
  - ... and 2 more failures.
- Test i2c_host_mode_toggle has 3 failures.
  - 17.i2c_host_mode_toggle.55652830418931539057521693707430695843176146416473641394244566037297990818190
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_mode_toggle/latest/run.log
```
  Job ID: smart:f2d85aea-730f-4d75-8f6d-1b95725a4fca
```
  - 29.i2c_host_mode_toggle.52261164313486326185167417440077346916396384950666349333838223756071823249208
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_host_mode_toggle/latest/run.log
```
  Job ID: smart:ce7d9e3f-3b6c-461e-8049-12b14a3fa648
```
  - ... and 1 more failures.
- Test i2c_host_stress_all has 3 failures.
  - 24.i2c_host_stress_all.105070932334128390030366332693029231207155408709407900057195163816434841364638
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:7b8676ae-ac5c-453c-9094-05f8cd0039c9
```
  - 30.i2c_host_stress_all.114919688150245103722567614130741929029595161700894322396712054797526315841970
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:86b77a7e-d17e-43de-a3cb-78d66cf649bf
```
  - ... and 1 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:

Test i2c_csr_bit_bash has 2 failures.

0.i2c_csr_bit_bash.10943897573621539491336486694387617091404286530648050812696998281694534461498
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @  61519472 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @  61519472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_csr_bit_bash.109753579986301484841089248130972013683990431213756865059002665139812155957133
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 930581129 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 930581129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_target_stress_all_with_rand_reset has 4 failures.

2.i2c_target_stress_all_with_rand_reset.55300102677347969652263306373013558674796369511619615453712328659308673760783
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 8266781354 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 8266781354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.i2c_target_stress_all_with_rand_reset.56813333398728060065612715912723634735230939601135576841461568762895001547473
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1540116874 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1540116874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 9.i2c_target_stress_all_with_rand_reset.51255991393316596729161309653325652607350283966858388012515927084389857433238
    Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1803185076 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 22 [0x16])
  UVM_INFO @ 1803185076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.i2c_target_stress_all_with_rand_reset.78552532834606678989288200630116869868091092226768013073111193334983948812162
    Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2703788349 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 2703788349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (i2c_glitch_vseq.sv:197) virtual_sequencer [i2c_glitch_vseq] timed out waiting for state: StretchAddr has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.110833530794342715693315474911378268879051483356575027881469460092577827619398
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 3771994196 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
  UVM_INFO @ 3771994196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.76980527908343505790908769240315202128212901040328210214365115732923009758603
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 1602717271 ps: (i2c_glitch_vseq.sv:197) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_glitch_vseq] timed out waiting for state: StretchAddr
  UVM_INFO @ 1602717271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 18.i2c_target_stress_all_with_rand_reset.76682234731410663934288255220822795031737964382545975094580374446688255453683
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10391501616 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10391501616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.i2c_target_stress_all_with_rand_reset.55952782914387947177729362138585973668597377358907294209082481608618048446119
    Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10041474767 ps: (i2c_target_smoke_vseq.sv:97) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10041474767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job i2c-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:
- Test i2c_host_stretch_timeout has 1 failures.
  - 14.i2c_host_stretch_timeout.46249717151650266834236675559877822064534503036533900848378921356594404497024
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stretch_timeout/latest/run.log
```
  Job ID: smart:9585305a-9a74-4d75-8625-5a3563d6eb90
```
UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 25.i2c_target_stress_all_with_rand_reset.47449754859255096442184403655907448927665390367555568384202004099718133586042
    Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1145940040 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1145940040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 32.i2c_host_stress_all.114509765073132482516516921437452784895908008394668034796949924366650365942977
    Line 5501, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 38543764566 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  direction  READ item mismatch!
  --> EXP:
  -----------------------------------------------
  Name              Type          Size  Value
```
UVM_ERROR (i2c_base_vseq.sv:977) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop has 1 failures:
- Test i2c_target_perf has 1 failures.
  - 41.i2c_target_perf.52412242080776591125713312570424124094108921270079771734037887699080251949870
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  35489647 ps: (i2c_base_vseq.sv:977) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set UnexpStop
  UVM_INFO @  35489647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 47.i2c_target_stress_all_with_rand_reset.63841689701242188316777959422488808013822291743456435978333957631205595163004
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10225343965 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x85686c94) == 0x0
  UVM_INFO @ 10225343965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```