I2C Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.546m	6.863ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	1.007m	14.728ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.810s	27.455us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.820s	47.036us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.800s	5.968ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.050s	1.291ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.490s	100.907us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.820s	47.036us	20	20	100.00
		i2c_csr_aliasing	2.050s	1.291ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	2.070s	111.990us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	55.197m	39.115ms	46	50	92.00
V2	host_maxperf	i2c_host_perf	28.328m	54.062ms	50	50	100.00
V2	host_override	i2c_host_override	0.730s	70.953us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.649m	17.327ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.746m	2.151ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.200s	330.351us	50	50	100.00
		i2c_host_fifo_fmt_empty	27.730s	515.791us	50	50	100.00
		i2c_host_fifo_reset_rx	11.880s	202.392us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.114m	10.165ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	34.690s	2.924ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.809m	8.537ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	8.520s	6.002ms	10	50	20.00
V2	target_glitch	i2c_target_glitch	11.750s	5.453ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	12.083m	44.560ms	0	50	0.00
V2	target_maxperf	i2c_target_perf	1.380s	131.122us	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.158m	1.587ms	50	50	100.00
		i2c_target_intr_smoke	8.740s	9.199ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.328m	10.049ms	50	50	100.00
		i2c_target_fifo_reset_tx	1.637m	10.082ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	43.128m	68.739ms	50	50	100.00
		i2c_target_stress_rd	1.158m	1.587ms	50	50	100.00
		i2c_target_intr_stress_wr	13.162m	29.235ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.500s	5.630ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	46.383m	39.361ms	44	50	88.00
V2	bad_address	i2c_target_bad_addr	5.960s	5.537ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	3.470s	2.115ms	50	50	100.00
V2	target_fifo_watermark	i2c_host_fifo_watermark	5.649m	17.327ms	50	50	100.00
V2	host_mode_config_perf	host_mode_config_perf			0	0	--
V2	host_mode_clock_stretching	host_mode_clock_stretching			0	0	--
V2	target_mode_txrst_on_cond	target_mode_txrst_on_cond			0	0	--
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	alert_test	i2c_alert_test	0.700s	82.631us	50	50	100.00
V2	intr_test	i2c_intr_test	0.760s	31.073us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.660s	156.976us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.660s	156.976us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.810s	27.455us	5	5	100.00
		i2c_csr_rw	0.820s	47.036us	20	20	100.00
		i2c_csr_aliasing	2.050s	1.291ms	5	5	100.00
		i2c_same_csr_outstanding	1.200s	61.554us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.810s	27.455us	5	5	100.00
		i2c_csr_rw	0.820s	47.036us	20	20	100.00
		i2c_csr_aliasing	2.050s	1.291ms	5	5	100.00
		i2c_same_csr_outstanding	1.200s	61.554us	20	20	100.00
V2		TOTAL			1242	1392	89.22
V2S	tl_intg_err	i2c_tl_intg_err	2.350s	314.955us	20	20	100.00
		i2c_sec_cm	0.960s	65.258us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.350s	314.955us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.422m	159.364ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.433m	8.978ms	0	50	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	100	0.00
	Unmapped tests	i2c_host_may_nack	19.410s	567.786us	50	50	100.00
		TOTAL			1472	1722	85.48

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	7	100.00
V2	36	30	25	69.44
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.50	97.12	91.38	97.66	83.58	94.37	98.67	91.70

Failure Buckets

UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 102 failures:
- Test i2c_target_perf has 49 failures.
  - 0.i2c_target_perf.66507423092267748337337908836175689083671854259487395883760365368545302863356
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  47029817 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @  47029817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.53785401572449778874956282018257812513603951780315741133376876976180748834615
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_ERROR @   7045282 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @   7045282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 47 more failures.
- Test i2c_target_stress_all has 29 failures.
  - 0.i2c_target_stress_all.90932264043454607251173721335584783618704467141617028412015178100611836611878
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 130206226 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 130206226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_stress_all.76909389605940022274725139479746372699159911550669039381065741012589466557430
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 890709390 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 890709390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
- Test i2c_target_stress_all_with_rand_reset has 24 failures.
  - 0.i2c_target_stress_all_with_rand_reset.16129161356910421034729764472032136919104669189989208692990268929133558405513
    Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 434803719 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 434803719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_stress_all_with_rand_reset.68374478457143491938132520279608497706437164911993443689675065992835994659714
    Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5339637289 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 5339637289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 58 failures:

Test i2c_host_stress_all_with_rand_reset has 45 failures.

0.i2c_host_stress_all_with_rand_reset.64826581556277004354164630149647078448243238296630157549109568494624382492014
Line 14191, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 57461792073 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 57461792073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.4569859762819160101785213408266297297731657425412708076383677223095592991509
Line 9490, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 43516333166 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 43516333166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 43 more failures.

Test i2c_target_stress_all_with_rand_reset has 13 failures.

5.i2c_target_stress_all_with_rand_reset.38747085476096416927201268208767931460344172421733735508100213117722775606650
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2339061381 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2339061381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_target_stress_all_with_rand_reset.61052811508156320985994351432193392302133360820142216218595240091494866949333
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11911417354 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11911417354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_ERROR (i2c_base_vseq.sv:985) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 55 failures:
- Test i2c_target_unexp_stop has 39 failures.
  - 0.i2c_target_unexp_stop.111161904155427673462667886830795613984848249923306014713660261536820923994596
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 755366358 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 755366358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.30224386655735068767146365153355856785394049312747616424428126134431799276943
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1621292472 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 1621292472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 37 more failures.
- Test i2c_target_stress_all has 16 failures.
  - 3.i2c_target_stress_all.60959537290551089914210090618941722148752510483305717098563751546007612507422
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 8638812170 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 8638812170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.i2c_target_stress_all.51908292955974967405277369324033869030201313720320605990588114291925657485515
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 13496011656 ps: (i2c_base_vseq.sv:985) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 13496011656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test i2c_target_stretch has 6 failures.
  - 8.i2c_target_stretch.94957312765712316747487507287306898114806004234459255570229305983774013560379
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stretch/latest/run.log
```
  Job ID: smart:b57f0c6c-108d-4adc-9316-0325561e05e9
```
  - 9.i2c_target_stretch.111831167575305337355438888690563264188632205200847328010688452129807870871324
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stretch/latest/run.log
```
  Job ID: smart:af9c1803-f8b7-4d82-970c-b477b00cd28d
```
  - ... and 4 more failures.
- Test i2c_host_stress_all has 3 failures.
  - 22.i2c_host_stress_all.96961223278613037634471588965687917454751322432849871927349008681641606066585
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:975c6d11-2e40-49ed-aaf2-20fda2c53f96
```
  - 41.i2c_host_stress_all.106451355574103100892138476660612360718825031760593524238347723167848992596604
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:d979ef89-7daf-4313-80c3-3c018eab39c3
```
  - ... and 1 more failures.
- Test i2c_host_stress_all_with_rand_reset has 4 failures.
  - 37.i2c_host_stress_all_with_rand_reset.83821247358252518136139025631137348555475799077788185169578946702625860609441
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0d0ce62b-2a35-45d4-9128-e3e124765d8b
```
  - 42.i2c_host_stress_all_with_rand_reset.37833576237019938061473134397383484739187123891927025524829723514891174804556
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:39126293-91df-4099-a6d5-9cf91f95acce
```
  - ... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 4 failures:
- Test i2c_target_stress_all has 3 failures.
  - 15.i2c_target_stress_all.53876348624798225465946978566431432992147875708785421694080955196128618604372
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 3245208867 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 4 [0x4])
  UVM_INFO @ 3245208867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.i2c_target_stress_all.43348217118609903555119132562135387334051778176075333812090342276067684686330
    Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 31720061719 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 7 [0x7])
  UVM_INFO @ 31720061719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 48.i2c_target_stress_all_with_rand_reset.26447493658478250677679717514599087480924776775021122653896058906826229287688
    Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3934466244 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (10 [0xa] vs 9 [0x9])
  UVM_INFO @ 3934466244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 4 failures:
- Test i2c_target_stress_all has 1 failures.
  - 27.i2c_target_stress_all.42408450574053759318530799768864770584709480811029870004699671505869200699887
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 3492227717 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3492227717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 28.i2c_target_stress_all_with_rand_reset.20098220141352315771874020936163847015830820768841059082792983808532136895589
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  36187463 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @  36187463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.i2c_target_stress_all_with_rand_reset.59341680608360409858498410892626512184175267577168632796436078165134594480723
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  42691409 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @  42691409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_perf has 1 failures.
  - 42.i2c_target_perf.67378431814685824846623726559614923815287484885280386507413441171457205961220
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_perf/latest/run.log
```
  UVM_ERROR @  17521630 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
  UVM_INFO @  17521630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 3.i2c_target_stress_all_with_rand_reset.97952200862735375535550049411425281454513798838935367565819395077473632466125
    Line 366, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 19524415384 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 19524415384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.i2c_target_stress_all_with_rand_reset.38642388912094778768055975855383243011982416543508835440352582428956936523745
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11588789301 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 11588789301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_unexp_stop has 1 failures.
  - 38.i2c_target_unexp_stop.93569689410064861957634509985383068130950003041546143038415673174201379497446
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 13599162856 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 13599162856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 4.i2c_target_stress_all_with_rand_reset.73889413144896779354518400748473795376488067840933728752082723553531057194654
    Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 11206395814 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 11206395814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 23.i2c_target_stress_all_with_rand_reset.72839795769963219186343416895726296696427301715532991622630184075660492899202
    Line 343, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all_with_rand_reset/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 35880394597 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 35880394597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 9.i2c_target_stress_all_with_rand_reset.27727898513678746165399264296131579722887973014949413944050460692992277810809
    Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2639663028 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (6 [0x6] vs 185 [0xb9])
  UVM_INFO @ 2639663028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.i2c_target_stress_all_with_rand_reset.99058477638823683937312800435864833697165071154823380794385617167772871544107
    Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7938008240 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (111 [0x6f] vs 217 [0xd9])
  UVM_INFO @ 7938008240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 11.i2c_target_stress_all_with_rand_reset.30518794964403175529255466016700346346692807406963112835373058532041587151082
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 916455284 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 916455284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.i2c_target_stress_all_with_rand_reset.57956233935483272764392431925450819627466479198166248515582901689455180850718
    Line 442, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46285627528 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 46285627528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_perf_vseq.sv:206) virtual_sequencer [i2c_host_perf_vseq] DUT not working as expected has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 6.i2c_host_stress_all.66016130356387096676073915213952943431767081075849862801028422727044595654589
    Line 1660, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 43374486215 ps: (i2c_host_perf_vseq.sv:206) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_host_perf_vseq] DUT not working as expected
  UVM_INFO @ 43374486215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1165) [stop_interrupt_handler] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 33.i2c_target_stress_all.52454429110227023441782926635158383849926959760931573584385805974722908930427
    Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 44559936763 ps: (i2c_base_vseq.sv:1165) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 44559936763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 46.i2c_host_stress_all_with_rand_reset.109440781852194564741335211779212867692747499237163739943263971270996342236208
    Line 3158, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11982442930 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (8 [0x8] vs 3 [0x3])
  UVM_INFO @ 11982442930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```