b29ffbb03c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.886m | 19.124ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 57.080s | 1.476ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.820s | 59.514us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.900s | 52.476us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.050s | 528.633us | 4 | 5 | 80.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.240s | 635.746us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.670s | 35.234us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.900s | 52.476us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.240s | 635.746us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 154 | 155 | 99.35 | |||
| V2 | host_error_intr | i2c_host_error_intr | 27.760s | 2.140ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 54.518m | 28.629ms | 45 | 50 | 90.00 |
| V2 | host_maxperf | i2c_host_perf | 48.052m | 46.961ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.770s | 31.068us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.629m | 20.695ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.782m | 5.270ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.290s | 131.355us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 31.010s | 2.227ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.330s | 855.349us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.180m | 4.630ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 53.580s | 1.451ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.046m | 2.467ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 9.586m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 10.770s | 38.969ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 22.561m | 36.366ms | 1 | 50 | 2.00 |
| V2 | target_maxperf | i2c_target_perf | 1.400s | 257.868us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.365m | 1.883ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 7.640s | 14.948ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 51.760s | 10.203ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.369m | 10.200ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 30.726m | 58.661ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.365m | 1.883ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 10.244m | 25.073ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.390s | 2.907ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 53.557m | 42.815ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.930s | 2.615ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.360s | 2.288ms | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.830s | 1.312ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 6.220s | 1.026ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 21.910s | 1.142ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.720s | 30.176us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.810s | 18.460us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.960s | 54.972us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.960s | 54.972us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.820s | 59.514us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.900s | 52.476us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.240s | 635.746us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.280s | 65.564us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.820s | 59.514us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.900s | 52.476us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.240s | 635.746us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.280s | 65.564us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 1380 | 1542 | 89.49 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.990s | 1.872ms | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.980s | 68.035us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.990s | 1.872ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 15.448m | 292.565ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 3.592m | 8.372ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 34.620s | 5.833ms | 50 | 50 | 100.00 | |
| TOTAL | 1609 | 1872 | 85.95 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 48 | 33 | 26 | 54.17 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.08 | 96.60 | 90.18 | 97.67 | 70.24 | 93.62 | 98.44 | 90.84 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 94 failures:
0.i2c_target_perf.42543842382664921904794097258314856723058135823300026277582675034625552779339
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 490992808 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 490992808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.98360463002159794558486774109310360569809598598624233024599658433435753972579
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 62016942 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 62016942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
2.i2c_target_stress_all.21596403562728281068456264035962379027125717765003165308949137139307167588528
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 134375757 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 134375757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.28212329251748166323745153442742835899887233029865847957021652614992903060720
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 30057884529 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 30057884529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
8.i2c_target_stress_all_with_rand_reset.108943079073986832197918171273217224931440825344085811372537891897651330646832
Line 356, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8372203774 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 8372203774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all_with_rand_reset.105032795455142250541556185973777509157841734673573837219865304157971419732510
Line 281, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11213236703 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 11213236703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:
0.i2c_host_stress_all_with_rand_reset.64056331680864817035977552370061498221474995593602718887635375575231771661828
Line 532, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 938748955 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 938748955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.68093529295981617186382804523725757375304630782240952753928214862855270305182
Line 1626, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1898435869 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1898435869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 40 more failures.
1.i2c_target_stress_all_with_rand_reset.32895656117840369927828929414574231402547573192831640989760249207448579023175
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2325433868 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2325433868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.24800349078754021647849154388901000025902386280976726405971563101109693235093
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 690476639 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 690476639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 41 failures:
2.i2c_target_unexp_stop.83257572397118293509924820934500177870734858787205265103516986196535935653734
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 80921329 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 244 [0xf4])
UVM_INFO @ 80921329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.48388331674590781170775648075766891248464914113368031479090782165995618852358
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 48164258 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 173 [0xad])
UVM_INFO @ 48164258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
5.i2c_target_stress_all.106320946293982265717752222449826484269086949934326781675171796417419250977851
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 17011295802 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 17 [0x11])
UVM_INFO @ 17011295802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stress_all.40798809104822172789580116904318717586315638955189552204081274928622957589614
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 131807609 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 15 [0xf])
UVM_INFO @ 131807609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
6.i2c_target_stress_all_with_rand_reset.77638583401624365525725419168425410866611169305634087671399106894653061623933
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36209871 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 221 [0xdd])
UVM_INFO @ 36209871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_stress_all_with_rand_reset.2732218546809470811699463612800001660901869965213973572444892991730361880049
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14951475237 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 167 [0xa7])
UVM_INFO @ 14951475237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 34 failures:
0.i2c_target_unexp_stop.36688249200363878145856140533554200833938696071486583860693389861455068837850
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1322804686 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1322804686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.29358681467578436605454123312325640964346269545432806900167717318040916478121
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 77610444 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 77610444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
0.i2c_target_stress_all.112334759406115791217335692100948108344540470394233421535606519145362460906632
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 704576982 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 704576982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all.43906033848514674601091959398562431749896888910901257332654729816080136518063
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 18427494665 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 18427494665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
0.i2c_target_stress_all_with_rand_reset.90938674096459497365411758153019419178218001624098021640285319611766803648709
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 57779661 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 57779661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.113480053113039361029500607997836469987949203184778835287374430810795308438764
Line 322, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21110851792 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 21110851792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
49.i2c_target_perf.63771295764812162417918797733502885651022966223055945656336260460905483461030
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_perf/latest/run.log
UVM_ERROR @ 87675116 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 87675116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
Test i2c_target_unexp_stop has 3 failures.
1.i2c_target_unexp_stop.55209311728516879162071734576625484339960976431084593454618868516827411095829
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
Job ID: smart:928e676f-51bc-43f8-a67b-6c6d38c71143
17.i2c_target_unexp_stop.71548331414761942801695922717171056992911288220152747446267048626349239043285
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_unexp_stop/latest/run.log
Job ID: smart:c5a67f39-5c21-4d8e-bcc5-9f9b14f54544
... and 1 more failures.
Test i2c_host_stress_all_with_rand_reset has 8 failures.
3.i2c_host_stress_all_with_rand_reset.2209919498935066386466591909717529112776543768876287505214380725568921662392
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:f30d0428-cff4-452f-a5d7-bc34c953b0ca
5.i2c_host_stress_all_with_rand_reset.91899386870635230404440526930487888822419919348116642875103291476589473938574
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:20a3f950-1f04-4c0c-b2b0-3c9639ba3876
... and 6 more failures.
Test i2c_target_stretch has 4 failures.
10.i2c_target_stretch.74412622927125386740456914020927703145656903117792548963624371076150008946341
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stretch/latest/run.log
Job ID: smart:0a36b94b-046c-47e7-bf49-097bb8f95ba1
16.i2c_target_stretch.111793801553605381627714709463581574491084562736836423972340680654056431258132
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stretch/latest/run.log
Job ID: smart:37fdc283-27d5-4fc1-bfcd-1f9c52a2eea4
... and 2 more failures.
Test i2c_target_stress_all has 1 failures.
12.i2c_target_stress_all.29347441934844522772426422009355836286428672299545171316837737218670247958028
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
Job ID: smart:7b9de63a-d96a-4d8e-9350-8c4bbc900a79
Test i2c_host_stress_all has 3 failures.
22.i2c_host_stress_all.106852798863752610886185954225504117590832247124119782550661135701091780326923
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
Job ID: smart:85165fd1-ed41-4c9d-bc7a-aa3917717203
45.i2c_host_stress_all.48334932572416940185824131169277589498238425073009856808651081640811793871635
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_host_stress_all/latest/run.log
Job ID: smart:13182139-08d1-47cb-accc-9907745cf6a0
... and 1 more failures.
... and 1 more tests.
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 8 failures:
4.i2c_target_unexp_stop.48453628698864202887581471862514279687582051755566581508060185715926187458832
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 798460621 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 798460621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.98730344030603419664937736365429524194005679215369699518466076485264963899336
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 759304873 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 759304873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
9.i2c_target_stress_all.61433976079076832240088958749090836760845635657703180809759374382506905868915
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 34575973972 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 34575973972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 6 failures:
Test i2c_target_unexp_stop has 3 failures.
14.i2c_target_unexp_stop.61653265792785338012621302317374414475756975583862654192266739399140420685606
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 222453055 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 10 [0xa])
UVM_INFO @ 222453055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.i2c_target_unexp_stop.108859361824271904043308782258209692061346749371948279543145716482962348601555
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 511816697 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 1 [0x1])
UVM_INFO @ 511816697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test i2c_target_stress_all has 1 failures.
19.i2c_target_stress_all.66594027400161531307461110441210383246810266448545094303413686339720612488086
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 12851317460 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 5 [0x5])
UVM_INFO @ 12851317460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 2 failures.
26.i2c_target_stress_all_with_rand_reset.23584071265811113765600795972317424007458170512967039211485523946351775112534
Line 357, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 82010329198 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (16 [0x10] vs 14 [0xe])
UVM_INFO @ 82010329198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.i2c_target_stress_all_with_rand_reset.593037804376901993450179459875744238075054890973476426606835239018351366577
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30662412 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 4 [0x4])
UVM_INFO @ 30662412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 4 failures:
4.i2c_target_stress_all_with_rand_reset.112577688903552395637504737762738272955377667854037923321196853163338781424695
Line 331, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5773097663 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (75 [0x4b] vs 67 [0x43])
UVM_INFO @ 5773097663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.36713443647719300919576607201067923314318747595669735018528997628949287213993
Line 281, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5135986609 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (135 [0x87] vs 134 [0x86])
UVM_INFO @ 5135986609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 3 failures:
Test i2c_host_stress_all has 2 failures.
8.i2c_host_stress_all.49831490083651960938664076962222914366655550540737433865418334322638975358953
Line 1734, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 6994603113 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
38.i2c_host_stress_all.10144065191078612520763407791129557723990227278506408497336256843504671702904
Line 4159, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 38029557265 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
Test i2c_host_perf has 1 failures.
13.i2c_host_perf.31445319249833293373415756671168362246319390502433590037687267166685696813198
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_perf/latest/run.log
UVM_ERROR @ 64009414 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:
0.i2c_same_csr_outstanding.28686747203338975294617964890299886669178109410961538004532023136565339802233
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 67292630 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x587e1778 read out mismatch
UVM_INFO @ 67292630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_same_csr_outstanding.115057111223591233435505549709041846020525081218750932852628116926482627636224
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 50588077 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x5ed90a78 read out mismatch
UVM_INFO @ 50588077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
3.i2c_csr_bit_bash.70502528874638634716373577416831399721004484427034755497872417506895336920171
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 441050970 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 441050970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 1 failures:
12.i2c_target_unexp_stop.74414217550644689083865962037544987382953471540678297432232885853103018194228
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 11566491012 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 11566491012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
13.i2c_target_unexp_stop.44369556876094529197911699885673849190168510849339546435173646635793001879451
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---