8cb25a6867| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.931m | 34.228ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 1.097m | 1.658ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.760s | 62.381us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.840s | 58.546us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.310s | 429.546us | 3 | 5 | 60.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.130s | 1.247ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.500s | 105.251us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.840s | 58.546us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.130s | 1.247ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 153 | 155 | 98.71 | |||
| V2 | host_error_intr | i2c_host_error_intr | 33.540s | 683.165us | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 57.514m | 17.080ms | 46 | 50 | 92.00 |
| V2 | host_maxperf | i2c_host_perf | 22.469m | 28.280ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.740s | 27.768us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.115m | 21.157ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.327m | 2.754ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.270s | 339.697us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 31.920s | 604.670us | 49 | 50 | 98.00 | ||
| i2c_host_fifo_reset_rx | 13.020s | 867.726us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.647m | 2.723ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 42.980s | 3.447ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.006m | 14.733ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 43.054m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 10.950s | 8.720ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 59.633m | 66.235ms | 1 | 50 | 2.00 |
| V2 | target_maxperf | i2c_target_perf | 1.430s | 1.286ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.228m | 22.960ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 7.290s | 1.519ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 48.800s | 10.166ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.385m | 10.118ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 44.117m | 69.034ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.228m | 22.960ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 10.433m | 23.414ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.190s | 1.700ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 56.876m | 20.742ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.450s | 5.294ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.420s | 1.298ms | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 7.030s | 1.441ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 6.150s | 1.083ms | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | target_mode_tx_stretch_ctrl | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.680s | 19.116us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.830s | 17.586us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.900s | 1.906ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.900s | 1.906ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.760s | 62.381us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.840s | 58.546us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.130s | 1.247ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.310s | 75.787us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.760s | 62.381us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.840s | 58.546us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.130s | 1.247ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.310s | 75.787us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1323 | 1492 | 88.67 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.600s | 594.907us | 16 | 20 | 80.00 |
| i2c_sec_cm | 1.040s | 59.481us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.600s | 594.907us | 16 | 20 | 80.00 |
| V2S | TOTAL | 21 | 25 | 84.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 16.360m | 94.318ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 18.019m | 17.933ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 20.840s | 1.927ms | 50 | 50 | 100.00 | |
| TOTAL | 1547 | 1822 | 84.91 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 38 | 32 | 22 | 57.89 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.92 | 96.57 | 89.88 | 97.67 | 69.64 | 93.62 | 98.44 | 90.63 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 95 failures:
0.i2c_target_perf.58225576498444898837250757307440465392082651738614842877245714056355880418846
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 205990824 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 205990824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.37195491056248169304397712547762852135595625916440058950212431970217109107645
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 142578330 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 142578330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 44 more failures.
0.i2c_target_stress_all_with_rand_reset.5165273393962914165867176274641302839826240952300595060079349245636411637359
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18087059 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 18087059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.24040390112819336599336676090909163846259891173683530395145986811060218287439
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 561102083 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 561102083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
1.i2c_target_stress_all.32934414849085833111640499352835016551756217497988621737391426861726498465550
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 5933703459 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 5933703459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.107113165887303375499052680941518674414043334652575754147354745731075427638133
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1672155499 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 1672155499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 51 failures:
1.i2c_host_stress_all_with_rand_reset.51827468418616156204040836950325198831340652308360889479402805753687916757970
Line 4128, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10827843126 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10827843126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.15843722339192607774703896679064098493548871974842141255496345808675641778532
Line 1646, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1055287110 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1055287110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 42 more failures.
1.i2c_target_stress_all_with_rand_reset.9460458193142160866163938821595654419878399171239458439959862419431138019650
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6682105021 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6682105021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.90615742808753845844753088292902696314160607353191863803760654304885060346950
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 162318444 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 162318444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 44 failures:
1.i2c_target_unexp_stop.60764422632996006081541907930044571513909325211734815263809739631701190933127
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 269754193 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 269754193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.72518084190177446107604481623665865078243616907551714543261648885592129151197
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 166905139 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 166905139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
3.i2c_target_stress_all.47689685631074034483570248757607706460634382106819608586919740094636156936143
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 341383337 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 341383337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all.14772800354295487930047550964747128100941640168791662953829390128670975221675
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 280352252 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 280352252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
5.i2c_target_stress_all_with_rand_reset.28630422360464088051649916634565064751943019049822903441218216802699861787012
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 267965984 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 267965984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.77816709107052424911973468039840263988570900478199475006408350399706426412432
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 152572812 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 152572812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
10.i2c_target_perf.20503185898075710331272117147152190878092396443903369776287595796133563723423
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_perf/latest/run.log
UVM_ERROR @ 16234136 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 16234136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_perf.22172391547343416907681742301035408929591984177991397941878353731389507483519
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_perf/latest/run.log
UVM_ERROR @ 46194645 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 46194645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 35 failures:
2.i2c_target_unexp_stop.76691861149722028276709982002294107204867236322941016247420578884389351959555
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 172841431 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 146 [0x92])
UVM_INFO @ 172841431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.26441725616081413164489757667243749826367580597275563024762684796432289267602
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 68960785 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 250 [0xfa])
UVM_INFO @ 68960785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
10.i2c_target_stress_all.79085079260079353861549024292314381350911472569892442035728134070886549506683
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 74993806 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 50 [0x32])
UVM_INFO @ 74993806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all.49762891510437777710169467135199134672094796338626804982822611425275026321144
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 360850164 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 23 [0x17])
UVM_INFO @ 360850164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
10.i2c_target_stress_all_with_rand_reset.15031192364305926511494248895983836680505560784124977269751271667441945441000
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 110906839 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 116 [0x74])
UVM_INFO @ 110906839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all_with_rand_reset.42856511784573365140426204441097164553086710045233399579083120446752145243724
Line 305, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8573904993 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 21 [0x15])
UVM_INFO @ 8573904993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
Test i2c_target_unexp_stop has 2 failures.
0.i2c_target_unexp_stop.45199910422158890948704434899293781536542594889346339278144705133827167518338
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
Job ID: smart:996e1e0a-5d05-47f3-9187-676b13101a0c
4.i2c_target_unexp_stop.55706277523562505842151366862123347145332747929067856614094083770770388673640
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Job ID: smart:130ec925-cbd6-4058-ac76-37991a5522d5
Test i2c_host_stress_all_with_rand_reset has 4 failures.
0.i2c_host_stress_all_with_rand_reset.65705689899579395050937293821331545460896861027853011968858005673722729748134
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:590e468c-6141-4558-8560-0efb360e551e
8.i2c_host_stress_all_with_rand_reset.25143561168582547976424363557290294679998351011162140993950027421574290867324
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:74bdf513-9675-4225-9ee7-b49f9a23de3b
... and 2 more failures.
Test i2c_target_stretch has 7 failures.
4.i2c_target_stretch.80952618528403270002400385086393989191499680785730037782110959589214774440318
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
Job ID: smart:180202c8-79b7-4081-8efe-09448be527aa
5.i2c_target_stretch.34511714434988063348603648891547616235268581082092206460009158947357596446729
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
Job ID: smart:6a83d25e-69fb-4f86-9ab5-15a5128f80f7
... and 5 more failures.
Test i2c_host_perf has 3 failures.
27.i2c_host_perf.38627421637357439902375166195531595486218790079118815415368399575304614136414
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_perf/latest/run.log
Job ID: smart:4afdc635-f90b-410d-a986-84d6f5656ea6
35.i2c_host_perf.66982674369939701434779662376308030958759505603734715753617938626966423783247
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_perf/latest/run.log
Job ID: smart:dd9bba84-be92-49f5-919c-628ef6766203
... and 1 more failures.
Test i2c_host_stress_all has 1 failures.
39.i2c_host_stress_all.68644566683922098723462475667963100916893471320344735613621845887153994087807
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_stress_all/latest/run.log
Job ID: smart:054079a6-b68d-414e-95b7-fa69766653aa
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 10 failures:
Test i2c_target_stress_all_with_rand_reset has 5 failures.
3.i2c_target_stress_all_with_rand_reset.45207412356535123926148232718108209398612890168973183743770912416817491119193
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1464419942 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 2 [0x2])
UVM_INFO @ 1464419942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.84937546636746875050967938902353725142587037610636052123350826046435427985458
Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10457155704 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 3 [0x3])
UVM_INFO @ 10457155704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test i2c_target_stress_all has 2 failures.
6.i2c_target_stress_all.50401595166278889089222632625034211230310350581226804651232957130715335753856
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2247282331 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 3 [0x3])
UVM_INFO @ 2247282331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_stress_all.22158075142877506858960526424434355095259909178807896838981455350974926936548
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 3463131625 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 4 [0x4])
UVM_INFO @ 3463131625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 3 failures.
34.i2c_target_unexp_stop.112790235031319112910214294706460280772432284585302168271361230121902749955272
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 88934235 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (20 [0x14] vs 8 [0x8])
UVM_INFO @ 88934235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.i2c_target_unexp_stop.37332777633462900621951372784114075908642491904805302846962441407440272901256
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 84827845 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 17 [0x11])
UVM_INFO @ 84827845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 7 failures:
Test i2c_host_stress_all has 3 failures.
0.i2c_host_stress_all.75139924073500293078147522396960724315124420245444980894032661567813165481088
Line 3487, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 6561105433 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
16.i2c_host_stress_all.63892682343744332003252377751975829477260541508865593416522178103982959920818
Line 4428, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 30871524539 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
... and 1 more failures.
Test i2c_host_stress_all_with_rand_reset has 2 failures.
7.i2c_host_stress_all_with_rand_reset.109834450797824010734104352756074590066797406034690381726354306497491813460202
Line 4681, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4678414113 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
18.i2c_host_stress_all_with_rand_reset.105696874721689162095513717161467542142712388230440846702527865225741705570103
Line 10543, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 42198995433 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
Test i2c_host_error_intr has 2 failures.
23.i2c_host_error_intr.2805894984149564891136441263254553320654751381245394874981392393558523261467
Line 1146, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 84162704 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
38.i2c_host_error_intr.12149698859094427170415824083046966610554379308044811264269236885984354120438
Line 332, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 215941344 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
UVM_ERROR (i2c_base_vseq.sv:989) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 4 failures:
10.i2c_target_unexp_stop.25634092605782081122257029792306906743118710356207139522345490210584782135970
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3274836856 ps: (i2c_base_vseq.sv:989) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3274836856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.i2c_target_unexp_stop.48011912146425254758872142783820112138054361080118899410659241123725885113190
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3102098735 ps: (i2c_base_vseq.sv:989) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3102098735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 3 failures:
0.i2c_tl_intg_err.57983553275301761846486529423340638460003026363422182636010228387870427998995
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 3850671 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 3850671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_tl_intg_err.83899740448874010493497570180011870429322905524223646391973812792034827018627
Line 335, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 206033952 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 206033952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 2 failures:
Test i2c_csr_bit_bash has 1 failures.
0.i2c_csr_bit_bash.47100490231050959509132022218112277549260100327151112670920890100792070956648
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 262787584 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 262787584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
8.i2c_target_stress_all.44400039895400913273963963876723540016801537450888278691712445906531712741122
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 175011437 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 175011437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
17.i2c_target_fifo_watermarks_tx.93490043506567113205833917755612379769608736241534403125453241156577340331530
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 722
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
48.i2c_target_fifo_watermarks_tx.48344177015708824416043998037297568763687137722060950370439228571894800910406
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 722
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test i2c_target_unexp_stop has 1 failures.
35.i2c_target_unexp_stop.113287930651729418185468860398371891274394986771084583324631044004389258797358
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_fifo_fmt_empty has 1 failures.
40.i2c_host_fifo_fmt_empty.109206040683420439344995007820556970940012524079456499185666777380585472635135
Line 1190, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest/run.log
UVM_FATAL @ 10000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 1 failures:
2.i2c_tl_intg_err.56272773151688570059184034827632946107552360193556521816170024728903880838152
Line 396, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 450681206 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 450681206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
3.i2c_csr_bit_bash.105793251949858343514446212868017133029558998259511112594710665848233775822230
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 429546327 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 429546327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
16.i2c_same_csr_outstanding.109984335902621006190839824559284319167186251590286263991714703283881135404940
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 302791777 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 302791777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---