2cf28c40e5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.070m | 16.449ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 47.910s | 5.762ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 52.063us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 27.639us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.330s | 1.635ms | 2 | 5 | 40.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.150s | 830.355us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.370s | 104.167us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 27.639us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.150s | 830.355us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 152 | 155 | 98.06 | |||
| V2 | host_error_intr | i2c_host_error_intr | 14.050s | 604.432us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 45.685m | 97.176ms | 45 | 50 | 90.00 |
| V2 | host_maxperf | i2c_host_perf | 56.923m | 27.109ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.730s | 41.526us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.167m | 20.562ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.656m | 10.816ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.250s | 140.214us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 28.240s | 537.603us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 14.810s | 234.452us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.592m | 5.663ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 48.560s | 1.005ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.304m | 5.092ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 29.897m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 11.520s | 4.472ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 41.441m | 47.745ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 1.070s | 116.327us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.325m | 5.703ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 6.860s | 1.348ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 49.720s | 10.108ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.377m | 10.111ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 46.557m | 71.660ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.325m | 5.703ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.595m | 18.350ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.620s | 1.387ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 45.793m | 32.609ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.720s | 4.502ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.340s | 2.233ms | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.910s | 1.344ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 6.630s | 1.028ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | target_mode_tx_stretch_ctrl | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.710s | 16.671us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.780s | 16.652us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.220s | 164.043us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.220s | 164.043us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 52.063us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 27.639us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.150s | 830.355us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.330s | 62.928us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 52.063us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 27.639us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.150s | 830.355us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.330s | 62.928us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1333 | 1492 | 89.34 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.640s | 312.181us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.990s | 85.595us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.640s | 312.181us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.108m | 34.470ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 18.482m | 32.117ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 31.310s | 2.841ms | 50 | 50 | 100.00 | |
| TOTAL | 1560 | 1822 | 85.62 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 38 | 32 | 26 | 68.42 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.98 | 96.59 | 89.81 | 97.67 | 69.64 | 93.62 | 98.44 | 91.05 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 99 failures:
0.i2c_target_perf.2277944794893729087819351359631709895552474549785528881396507103828119466165
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 188799482 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 188799482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.71268995422982780632636782828307515761040159311142360505592914945001432774057
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 190532522 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 190532522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.i2c_target_stress_all.3285199390731919267878205414436155269349751717726740440911587431764626172412
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 159310216 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 159310216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all.24355712860274256991464722964509320650457532256421709899560411216864257739358
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2480560862 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 2480560862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
2.i2c_target_stress_all_with_rand_reset.47700341772322356466805879657438722750562291585049607975039247220121913127305
Line 350, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37551804617 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 37551804617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.25969322403743661360303663328804060265347187887524720075521437226267528735748
Line 321, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 46223441731 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 46223441731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 50 failures:
0.i2c_host_stress_all_with_rand_reset.110911528174766360886039784295786006614946183449270042879330546671446358037122
Line 5752, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27888354732 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 27888354732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.79636154824110481985615761677890944658672474873767464096598228355299688423110
Line 2156, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10327943240 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10327943240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 41 more failures.
0.i2c_target_stress_all_with_rand_reset.3487946903450232396025226665974801331921640509537284780714616255936242376916
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 465613888 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 465613888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.93240347759204692415327047479860848482179314974376021063509322197689857779291
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2394989598 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2394989598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 38 failures:
0.i2c_target_unexp_stop.77626225853678550259978842868488251173120657209745014788841429532996032818602
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 68653276 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 189 [0xbd])
UVM_INFO @ 68653276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.84302566684929845535878130908964505595661903865127631358736987363913245311707
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 126664788 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 71 [0x47])
UVM_INFO @ 126664788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
4.i2c_target_stress_all.80480879286021774116281575044861499110308744552518512960052071859662623952360
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 11867716517 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 230 [0xe6])
UVM_INFO @ 11867716517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all.78164194833546368790653578088458584831210256307112640001985639014545613270921
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 137582701 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 107 [0x6b])
UVM_INFO @ 137582701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
10.i2c_target_stress_all_with_rand_reset.82429435233194254826910889105087238451292911471837179491685169214060361667165
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 241263033 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 142 [0x8e])
UVM_INFO @ 241263033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_stress_all_with_rand_reset.21580408863972384859208448942884575721682058409290913905002239673887793536764
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 211511206 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 28 [0x1c])
UVM_INFO @ 211511206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 34 failures:
2.i2c_target_stress_all.11732157490897505572080124431052733275021000123061727458259240910693170769140
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 733796071 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 733796071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all.73003350316771801612728037502134027581551471573483120209633936008011916426498
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 42500873138 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 42500873138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
4.i2c_target_unexp_stop.106015803757179938657613831845074880188441726473384256624301113716263436448780
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 95264105 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 95264105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.65864103001810808477925824565163780971567164441732799950560364266545830485536
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 335960934 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 335960934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
7.i2c_target_stress_all_with_rand_reset.36176605998463041492876931352576711502798944746729631104704542106671524929434
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21105847 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 21105847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stress_all_with_rand_reset.51835649456505245225957106488393052289920431989344523459125347746277886582536
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 134590644 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 134590644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
1.i2c_host_stress_all.86459736436406257583973957152461984815930926522694621449614250201072934105200
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:de50713f-4ca0-4b51-83f2-eb51b397cfbc
7.i2c_host_stress_all.112101439780849428739958869798459637409947180288717796261591734494826490353981
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
Job ID: smart:fd8a46c8-1c7a-4b10-b7c2-6095f6e2475c
... and 2 more failures.
3.i2c_target_stress_all.50657869569621006303967130844185190290502364655393597441801396369125828682648
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
Job ID: smart:a9604b5e-4493-4487-abd9-e22c4dd3af2c
16.i2c_target_stress_all.38792594230208500933751481235955639469291260517510695350337744516053752898755
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
Job ID: smart:277f7727-9996-4ef2-b376-0001fc3cf3b3
... and 1 more failures.
14.i2c_host_stress_all_with_rand_reset.62972821228979711662779963837022930447580383068827382040771337091619740470249
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:a8ba4358-9261-4dd8-8807-bf569e93accf
18.i2c_host_stress_all_with_rand_reset.61995758511567933405293843124888429154340155846174540232429800359343866958134
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:33265c3e-41ca-4cf4-bcc9-fbad553c0d91
... and 3 more failures.
18.i2c_target_stretch.18509333581166699234641462593208061760401537172829994484721341469827157728727
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stretch/latest/run.log
Job ID: smart:ad0dfa5e-138f-4050-b502-a296eb7fe688
23.i2c_target_stretch.11602342472597942203640963858904332628139263156307305847127005781605735901556
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stretch/latest/run.log
Job ID: smart:2847daa5-7265-4896-8dc8-2cdfb35c8f06
... and 1 more failures.
30.i2c_target_unexp_stop.62030417884784573127850049292300087433143106131059847659619656498257316653066
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_unexp_stop/latest/run.log
Job ID: smart:b80b11be-eb4a-4275-9b48-403f03dfe04c
32.i2c_target_unexp_stop.93246676129775681718400981727333933618972331964763611321472934040648173174032
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_unexp_stop/latest/run.log
Job ID: smart:51eb49f9-f8c4-4744-b353-27dff563fa74
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 7 failures:
3.i2c_target_unexp_stop.7751863846299503680310554249183796290772129208946878865347270693108755728368
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_unexp_stop.12199423946942338203528544246285611865696532594048469458969785375030284588762
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
40.i2c_host_perf.94336318498198274287729152518140343212682238888131463453239187511489254330822
Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:989) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 5 failures:
18.i2c_target_stress_all.87918848444414486321822902598532980862614322054991159824226178500672990852950
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 740318343 ps: (i2c_base_vseq.sv:989) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 740318343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.i2c_target_stress_all.58098734612124529790518774564441033099206985764464310984215524583122619829407
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 747812302 ps: (i2c_base_vseq.sv:989) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 747812302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
29.i2c_target_unexp_stop.103542518249017676938722958855101607145940576110047789360863352522089565946117
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3158202822 ps: (i2c_base_vseq.sv:989) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3158202822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.i2c_target_unexp_stop.104345056646881904779288493949742095097621498393698799364892851512752993226572
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 777208513 ps: (i2c_base_vseq.sv:989) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 777208513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 3 failures:
Test i2c_target_unexp_stop has 2 failures.
2.i2c_target_unexp_stop.99648078059558334576590769760804187329565910668498730704858440525828434998025
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 560478765 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 1 [0x1])
UVM_INFO @ 560478765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_target_unexp_stop.35102752715443838898788502218985807925104537217850414996695889931501599460127
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 117455745 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 5 [0x5])
UVM_INFO @ 117455745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
15.i2c_target_stress_all_with_rand_reset.80475223422580951156100602798466366480793555204835496527879000854668613354906
Line 550, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26406450853 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 8 [0x8])
UVM_INFO @ 26406450853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 2 failures:
0.i2c_csr_bit_bash.57226545749272897317322188147363472438261455536458522438089995522478592644106
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 106118613 ps: (i2c_fifos.sv:309) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 106118613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_csr_bit_bash.78581479732283806744490002789944981694822335051327009284725749277887393594110
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 305778034 ps: (i2c_fifos.sv:309) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 305778034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
11.i2c_target_stress_all_with_rand_reset.12563573364377125679963984939609058244699338424348010567297733838837224367243
Line 390, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23280022919 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (134 [0x86] vs 135 [0x87])
UVM_INFO @ 23280022919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.i2c_target_stress_all_with_rand_reset.40928743894818141889353814475922304573899916070288121894399721972408011296617
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1590952341 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (204 [0xcc] vs 211 [0xd3])
UVM_INFO @ 1590952341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 2 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
38.i2c_host_stress_all_with_rand_reset.104976640461010358761817045638712928883297723550143891750430486067632592476256
Line 646, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 469787871 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
Test i2c_host_stress_all has 1 failures.
41.i2c_host_stress_all.4842346384931647448323406196525326284673280518263612495031834070207536781086
Line 3944, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 10959226885 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
4.i2c_csr_bit_bash.67770676560456619452220084996576248648687331687174158645055013071730901325889
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 302731382 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 302731382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
8.i2c_target_stress_all_with_rand_reset.44879334626478692763907955372428083721032159185683280361283913333001888751890
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12511332119 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x8ed77494) == 0x0
UVM_INFO @ 12511332119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
29.i2c_host_stress_all_with_rand_reset.61943486049448664153029065912447229849875740088778420215093836415006398867206
Line 5397, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 61169531683 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
UVM_INFO @ 61169531683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---