1579f6a912| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.930m | 4.656ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 1.136m | 1.572ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.780s | 21.581us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.850s | 29.302us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.780s | 1.683ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.320s | 541.162us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.410s | 31.362us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.850s | 29.302us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.320s | 541.162us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 153 | 155 | 98.71 | |||
| V2 | host_error_intr | i2c_host_error_intr | 14.280s | 1.383ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 59.333m | 62.375ms | 41 | 50 | 82.00 |
| V2 | host_maxperf | i2c_host_perf | 46.057m | 48.560ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.750s | 19.801us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.294m | 11.200ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.309m | 5.212ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.210s | 163.944us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 28.710s | 560.076us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.530s | 891.033us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.722m | 11.316ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 39.050s | 868.192us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.140m | 2.751ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 22.050m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 10.890s | 9.514ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 9.660m | 40.961ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 1.140s | 81.204us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.204m | 1.687ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.110s | 1.706ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.467m | 10.083ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.506m | 10.048ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 11.342m | 56.671ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.204m | 1.687ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 9.723m | 24.213ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.700s | 1.623ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 56.411m | 41.890ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.980s | 2.792ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.110s | 852.227us | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_host_fifo_watermark | 7.294m | 11.200ms | 50 | 50 | 100.00 |
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | target_mode_tx_stretch_ctrl | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.700s | 28.247us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 17.748us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.110s | 61.613us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.110s | 61.613us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.780s | 21.581us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.850s | 29.302us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.320s | 541.162us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.210s | 73.612us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.780s | 21.581us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.850s | 29.302us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.320s | 541.162us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.210s | 73.612us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 1222 | 1392 | 87.79 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.420s | 514.200us | 17 | 20 | 85.00 |
| i2c_sec_cm | 1.010s | 475.776us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.420s | 514.200us | 17 | 20 | 85.00 |
| V2S | TOTAL | 22 | 25 | 88.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.739m | 20.295ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 4.853m | 7.479ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 27.750s | 2.508ms | 50 | 50 | 100.00 | |
| TOTAL | 1447 | 1722 | 84.03 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 5 | 71.43 |
| V2 | 36 | 30 | 23 | 63.89 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.03 | 96.59 | 89.81 | 97.67 | 70.24 | 93.62 | 98.44 | 90.84 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 90 failures:
0.i2c_target_perf.73256177693177301954485246461293334600458563337545544166257241731420638746884
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 26988446 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 26988446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.76354866622816090983602748665584195414746218479348744437200097195127201667057
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 69101322 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 69101322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
0.i2c_target_stress_all.22305147337023390221206911011857159259213436601163120026953568457359475969043
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 187167454 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 187167454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.82797232782818267441854495977629122876279659867827039313888020660817315630797
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2722778814 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 2722778814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
0.i2c_target_stress_all_with_rand_reset.19494623558513988712233806115957682893083708036727592899010583191288599470054
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 110027525 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 110027525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.26309746812100600239547331165213603345326625670246417117773693005386678495871
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2889964635 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 2889964635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 58 failures:
0.i2c_host_stress_all_with_rand_reset.26143581286065155989066526701870335999152795323385277434537633259093858613176
Line 2944, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 35326826785 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 35326826785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.18204227817053283870948828377445405874374445260101834635499605313051776793760
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 168630096 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 168630096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 45 more failures.
2.i2c_target_stress_all_with_rand_reset.55807344537756290871090241973338855641651452746630966415857528509965173530821
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1141213268 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1141213268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.36871635537754201378799229884570422391352961682046311059260083979557100598815
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1548550002 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1548550002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 40 failures:
1.i2c_target_stress_all.50360650970322112893880799933583896133132748280612923876960845920466024962596
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 16080032944 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 87 [0x57])
UVM_INFO @ 16080032944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.16652730716436519812302253672808259596870025061877343100986803339919605695016
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 214940828 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 110 [0x6e])
UVM_INFO @ 214940828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
2.i2c_target_unexp_stop.63969125305128610654317168053405714641745844924123877448775430628169313154139
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 360386613 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 193 [0xc1])
UVM_INFO @ 360386613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.55059835018442061377710911476660961543019086018269440549763610798867996564973
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 48358172 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 133 [0x85])
UVM_INFO @ 48358172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
6.i2c_target_stress_all_with_rand_reset.115532123717810932082638317890711148254510945663409596037384410321171283354064
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 35925777 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 76 [0x4c])
UVM_INFO @ 35925777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_all_with_rand_reset.8357431951077529745814566492148864562817109632391697775261240860422517183853
Line 307, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11629253936 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 228 [0xe4])
UVM_INFO @ 11629253936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 33 failures:
1.i2c_target_unexp_stop.18505453955129048248796317793598349219467503490465496445747100040046716917658
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 444689978 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 444689978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_unexp_stop.65831250580704274271719702607324097417059957849465994715310911844470203211102
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1429135066 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1429135066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
10.i2c_target_stress_all.40494801884893281847973611701328152183029662965134122829462465850763535031412
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 331467419 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 331467419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_stress_all.51078605432542088151251801411980582085140849457903627935272853629892103303781
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 16688821147 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 16688821147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
12.i2c_target_stress_all_with_rand_reset.58665370348900617694675870174515031942055120413893287172815739430394455726915
Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13493777158 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 13493777158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stress_all_with_rand_reset.6049379483156463015878421639535815484979146688084974402687469212042539955114
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 326087128 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 326087128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
39.i2c_target_perf.71683402615406687499046630702861319072143331026810387298001471249287222996169
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_target_perf/latest/run.log
UVM_ERROR @ 62418461 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 62418461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
Test i2c_host_stress_all has 5 failures.
1.i2c_host_stress_all.74331289491383905399244482932045441889537543878209470460697047063566580057970
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:71e351dd-7a7b-48b8-af86-0d31b2332488
9.i2c_host_stress_all.71566474963583012418450102144895965028882138543051259846156502786830843150639
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
Job ID: smart:07e4c519-22e5-4951-9210-7dfe4fbb6ec3
... and 3 more failures.
Test i2c_target_stretch has 6 failures.
1.i2c_target_stretch.104369578932135013913111001036678749395640221785848219569963300995495428143039
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
Job ID: smart:3b987afb-b2e4-4649-b0fd-d9370dd9ff55
3.i2c_target_stretch.45747510625366273105383635658809586231254944063019713173322208639591315800670
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
Job ID: smart:695dcc9b-de5a-4d88-99c7-d76348e2c0f3
... and 4 more failures.
Test i2c_target_stress_all has 2 failures.
4.i2c_target_stress_all.50063601200135586350292137885016850483568671775686973850298807289672385788129
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
Job ID: smart:5309f0d2-7b5e-4bbb-a566-1ba5167f5685
41.i2c_target_stress_all.107377226328552426073796537071054136904599651241958184562180378286341194691268
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_all/latest/run.log
Job ID: smart:90eedeb3-ac2c-44d5-9386-850084a1a976
Test i2c_host_stress_all_with_rand_reset has 3 failures.
16.i2c_host_stress_all_with_rand_reset.111052632519722400319394282114783299168813650081503677324416985453673090127046
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:f3f23e5c-095e-4033-beb4-91e7d3e84d05
22.i2c_host_stress_all_with_rand_reset.4237099086128958026811942263811625698279562886403029486045985361040253101157
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ef34cb67-e196-4470-9f4d-5ea986b2e6e9
... and 1 more failures.
Test i2c_host_perf has 2 failures.
20.i2c_host_perf.40906728780879476651595868022663376224953558817671664090858988130712864796142
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_perf/latest/run.log
Job ID: smart:8ac96cfa-1c4e-45de-8991-28eece6aaf6d
32.i2c_host_perf.76129807327534702374307708442332307092129710683813723942289988615974760023136
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_perf/latest/run.log
Job ID: smart:0ad247bd-cc17-4b42-8b28-4bb00f48a460
... and 1 more tests.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 9 failures:
0.i2c_target_unexp_stop.21853805332371210253901483727012025631600832558466861964053395478265051176877
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 109386526 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (2 [0x2] vs 1 [0x1])
UVM_INFO @ 109386526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.113575915482871446207151692608489681430865141380076206744317269624909585917134
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 455731048 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 8 [0x8])
UVM_INFO @ 455731048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
1.i2c_target_stress_all_with_rand_reset.109537570473502417141848080828753203057587862323649123992955636474542289262603
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1311906460 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 12 [0xc])
UVM_INFO @ 1311906460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.96818108226847559538497299313805956620209080531772054395780360285762204371824
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9442052425 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (22 [0x16] vs 20 [0x14])
UVM_INFO @ 9442052425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
9.i2c_target_stress_all.97399415559472166624899634360992465108697560761061114537202557528413070123136
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 17274963201 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 5 [0x5])
UVM_INFO @ 17274963201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:990) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 6 failures:
7.i2c_target_unexp_stop.13954955184575933068855646542930927154661787167842123999979733306599646897968
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3805157929 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3805157929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_unexp_stop.20213349410965600054390076580480627050517263266435467185023833995114716687460
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 714136077 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 714136077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
38.i2c_target_stress_all.109447569074640371715455816267440254105914524227758605452824606707218470504173
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 3216336869 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3216336869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.i2c_target_stress_all.47880325138240296724462824663277248315019017589636353926506528894199998006212
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2012053286 ps: (i2c_base_vseq.sv:990) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2012053286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 5 failures:
Test i2c_host_perf has 1 failures.
6.i2c_host_perf.20087583675299855800009294087689817881931508974676242980013041715410935689111
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_perf/latest/run.log
UVM_ERROR @ 350131682 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
Test i2c_host_stress_all has 4 failures.
19.i2c_host_stress_all.4962218265734252316793477923546822006358334369839996955351347878844228795136
Line 3803, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 32259359235 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
28.i2c_host_stress_all.66658021933307820550965380336350557545477510352213541674157660399987648049634
Line 10871, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 84532263148 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
8.i2c_target_unexp_stop.38570221598680411496362028747371275030382777944394117592222401322817886377395
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.99205218221114643147894598361364940131804791448252347889545454694466940714841
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 3 failures:
Test i2c_tl_intg_err has 2 failures.
7.i2c_tl_intg_err.29582343420270988038200862110907177453992757850958134610427654785301194712136
Line 302, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 213565417 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 213565417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_tl_intg_err.68392432154271619545245460900134717001129246694887503354101755281813232707106
Line 298, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 176450329 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 176450329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_csr_mem_rw_with_rand_reset has 1 failures.
12.i2c_csr_mem_rw_with_rand_reset.54756203177392943649824150604632596162266243625309322381555033125592588838730
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 19300128 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 19300128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
12.i2c_same_csr_outstanding.51822428162853046372360692346886161864546886876508768481773140502614817386775
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 19071498 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 19071498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_same_csr_outstanding.43645643420725434099148014883608908085281397183284371170807799053010347911499
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 80256473 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 80256473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 2 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
17.i2c_target_stress_all_with_rand_reset.15191649932076286370822817187306547482878947486462681870832783938734368830367
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10263428568 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10263428568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 1 failures.
31.i2c_target_unexp_stop.77118777832094858724165484800875966442075716177013773357123964799974571120175
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 11018532762 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 11018532762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 1 failures:
3.i2c_tl_intg_err.37859351444452656967204469007877668690715200219260994514503670853436119383797
Line 363, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 104523473 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 104523473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
3.i2c_csr_bit_bash.106871077674307714459020726924898540523810053221501417790222572923512162621561
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 243058937 ps: (i2c_fifos.sv:315) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 243058937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
16.i2c_target_stress_all_with_rand_reset.43809286565111938144885579591744401363216284622664790387612268790994057990061
Line 359, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6411397295 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (143 [0x8f] vs 87 [0x57])
UVM_INFO @ 6411397295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
26.i2c_target_stress_all_with_rand_reset.70920791513110231391873773009666971242103432212882547604162835016774439110032
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10527228292 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x6555514) == 0x0
UVM_INFO @ 10527228292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---