01a208901a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.733m | 8.458ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 52.370s | 3.578ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 24.226us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.870s | 43.393us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.100s | 680.050us | 2 | 5 | 40.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.030s | 270.926us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.480s | 101.170us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.870s | 43.393us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.030s | 270.926us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 152 | 155 | 98.06 | |||
| V2 | host_error_intr | i2c_host_error_intr | 12.930s | 306.685us | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 45.044m | 227.231ms | 40 | 50 | 80.00 |
| V2 | host_maxperf | i2c_host_perf | 32.397m | 47.847ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.720s | 27.237us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.091m | 5.119ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.541m | 25.640ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.310s | 148.025us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 32.800s | 4.130ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.060s | 209.326us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.739m | 11.194ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 46.810s | 2.037ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.143m | 9.276ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 27.351m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 10.510s | 2.050ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 12.160m | 30.300ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 1.070s | 75.579us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.043m | 1.377ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.310s | 9.874ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 50.520s | 10.153ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.378m | 10.133ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 34.946m | 63.325ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.043m | 1.377ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 9.417m | 24.212ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.400s | 1.408ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 50.702m | 40.878ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.060s | 2.444ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.360s | 1.269ms | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 7.130s | 1.518ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 6.040s | 1.037ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | target_mode_tx_stretch_ctrl | 0 | 0 | -- | ||
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.700s | 39.868us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 78.578us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.250s | 634.352us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.250s | 634.352us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 24.226us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.870s | 43.393us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.030s | 270.926us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.360s | 73.202us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 24.226us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.870s | 43.393us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.030s | 270.926us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.360s | 73.202us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1323 | 1492 | 88.67 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.400s | 86.662us | 16 | 20 | 80.00 |
| i2c_sec_cm | 1.120s | 218.721us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.400s | 86.662us | 16 | 20 | 80.00 |
| V2S | TOTAL | 21 | 25 | 84.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 19.771m | 50.001ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 18.761m | 600.000ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 22.670s | 1.092ms | 50 | 50 | 100.00 | |
| TOTAL | 1546 | 1822 | 84.85 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 48 | 32 | 23 | 47.92 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.06 | 96.60 | 90.18 | 97.67 | 69.64 | 93.62 | 98.44 | 91.26 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 93 failures:
0.i2c_target_perf.81537388170707010002494319015134088301960591000884030879291742469047237991282
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 28906724 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 28906724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.95246527976090771321378443535545644580283794100830389920004158406243398185364
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 47595398 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 47595398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
1.i2c_target_stress_all_with_rand_reset.43659023410154041701117353888980803081300230508227472146443802812957857780422
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4800512654 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 4800512654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.9104661698650012073790961951907207080652445044975731580948796988359524870511
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 72632287 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 72632287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
2.i2c_target_stress_all.95349190585219362835641970182989752012017517994517858121929330799531355848039
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 24777517960 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 24777517960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all.29564384310054156588234238663278742857172739985745773238823998462581334820104
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 6940248149 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 6940248149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 49 failures:
0.i2c_host_stress_all_with_rand_reset.87046726736869475890585545724459815361666422359303020285507342516837271996081
Line 8831, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 75837212399 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 75837212399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.82888239190560219384190817435891837023627733370003645770127651044849907634240
Line 3647, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11191773223 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11191773223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 41 more failures.
4.i2c_target_stress_all_with_rand_reset.57932893786057506495719852598714929270373841843929072874637511785460612930147
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7681892673 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7681892673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_stress_all_with_rand_reset.58788974456053541022181627915854067836966712367114450576785764406852207562263
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 558921911 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 558921911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 41 failures:
1.i2c_target_unexp_stop.38502869573272089764270072176623111036737099327618434866452926030487742225129
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 167261770 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 167261770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.28762376442643819377498939616870075633845716560018834710451131262730980632792
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 247963225 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 247963225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
5.i2c_target_stress_all.41630340664678822214060810150465072919764959404465319525833945842391439096897
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 17073653071 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 17073653071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all.73886557422797104851426132024649295709085880123164340360436230568908563681516
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 7382062136 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 7382062136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
7.i2c_target_stress_all_with_rand_reset.50509243201560946754364618783286572939664022882678727650896448487509045955068
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 78108462 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 78108462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.74506644957454482146417497610181180256481621834438062440613154474295690341845
Line 323, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15465709802 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 15465709802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
9.i2c_target_perf.76628476414477263949621040427313548752995819338931229660536854360896656233890
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_perf/latest/run.log
UVM_ERROR @ 65138281 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 65138281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 33 failures:
0.i2c_target_stress_all.86428493516594957598826871616062859007320781785648441762721731045767645312773
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 21452779712 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 92 [0x5c])
UVM_INFO @ 21452779712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all.28142707751934759098611089197724459734146520053053604837435080520201872199678
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 7432764844 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 157 [0x9d])
UVM_INFO @ 7432764844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
2.i2c_target_unexp_stop.106141668335741740685093078215401425644591081421150024531309190240061317983714
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 50203966 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 25 [0x19])
UVM_INFO @ 50203966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.94396439997590959738287703875623218955362777758020972985333832266621737807016
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 510888822 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 156 [0x9c])
UVM_INFO @ 510888822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
10.i2c_target_stress_all_with_rand_reset.80755389354071852783417482216124373773993468464124664523904142404005717460405
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1240020510 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 213 [0xd5])
UVM_INFO @ 1240020510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.i2c_target_stress_all_with_rand_reset.85643440166719993878363979114432396986450202134787631864820791309020097382542
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 825106621 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 29 [0x1d])
UVM_INFO @ 825106621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 27 failures:
5.i2c_host_stress_all_with_rand_reset.33626330938055905756681055251807938846763447398376039805448838735043288376765
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:3598164b-c67e-42ed-9431-7f2848875455
10.i2c_host_stress_all_with_rand_reset.78825902408247281509227181595048805810019979153802260748989897109860417989928
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e2a32797-5649-4264-9778-79b6f5395a47
... and 5 more failures.
6.i2c_target_stress_all.2766128716829544087115858780413060179070788416893915324998776535873970959239
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
Job ID: smart:28972040-3db2-4e80-b318-b9e2ac895de6
7.i2c_target_stress_all.63991542872112734619863158242963548107698615239743813139945661771621076603615
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
Job ID: smart:0b794198-498f-467d-9697-b3d3c0cab46b
... and 2 more failures.
7.i2c_host_perf.100503602026922734225601432959994187594844009881385502112269294795338247222059
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_perf/latest/run.log
Job ID: smart:e3598d43-48c1-4609-a10e-5eb1fe78792a
27.i2c_host_perf.62783490105386130774514186967153420932079425235184073052149860041087182922959
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_perf/latest/run.log
Job ID: smart:d20b0e70-0b01-403c-b33c-fd2d5cd9010f
... and 1 more failures.
9.i2c_target_stretch.8970689842253947262026924287348369333468438064741870791035491023753935373072
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stretch/latest/run.log
Job ID: smart:ab10677b-bd16-4f06-bf74-6f45f236b70e
19.i2c_target_stretch.27954803887958796116609561358089428506103880626823668589496173695906041251331
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stretch/latest/run.log
Job ID: smart:513805ae-ded2-44ea-ae8b-0ad71abba260
... and 1 more failures.
11.i2c_host_stress_all.79206412952046740695663238857834973063382720429383735497951949474891626085315
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
Job ID: smart:9e247689-fc88-4676-b1f8-e6ea3f129ec5
23.i2c_host_stress_all.76833183053098150969856666683718019052539118027841751224821185396141647066065
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
Job ID: smart:78c4f39d-6f23-41ce-b092-d4c7c90ae114
... and 5 more failures.
UVM_ERROR (i2c_base_vseq.sv:989) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 7 failures:
0.i2c_target_unexp_stop.3053137424420704333844802214123598545260756938725346227470817018001657555875
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 784074443 ps: (i2c_base_vseq.sv:989) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 784074443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_unexp_stop.23507619625751135085869643743461937970651160832438571843966064803187498182527
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 5321404103 ps: (i2c_base_vseq.sv:989) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 5321404103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 4 failures:
32.i2c_host_stress_all.10096563777820687876198808771727884479755831965212838203851531203352058096044
Line 11449, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 62496324577 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
33.i2c_host_stress_all.90496343276905279417915333235754851248740500173490091511011682844270855650678
Line 761, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 1398215625 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
... and 1 more failures.
46.i2c_host_error_intr.77502214713867081963771141105385325010384283600729945411279935253306210518423
Line 692, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 41769886 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
0.i2c_target_stress_all_with_rand_reset.76949378403209434847675145072490725022393024521691451622582157692776625168802
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13064068385 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x86103f14) == 0x0
UVM_INFO @ 13064068385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_target_stress_all_with_rand_reset.96899961524311181193110180461783805777614513873860023758595711621480025572603
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10194932897 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xf1e1e394) == 0x0
UVM_INFO @ 10194932897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 3 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
3.i2c_target_stress_all_with_rand_reset.41746825155183119063991348182374592120287443814054007495470294407603952190838
Line 336, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27976275771 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (2 [0x2] vs 4 [0x4])
UVM_INFO @ 27976275771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 1 failures.
19.i2c_target_unexp_stop.5180155311749675231189781049114167982562360637738941340248442252674514716532
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 129036310 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 1 [0x1])
UVM_INFO @ 129036310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
44.i2c_target_stress_all.102342326190079554159045175948429159352766761363111469380665216695495921410094
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2848751798 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 2 [0x2])
UVM_INFO @ 2848751798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test i2c_target_unexp_stop has 2 failures.
4.i2c_target_unexp_stop.70875487230379595434034057580213564692620565913395891661189315319129354309131
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.i2c_target_unexp_stop.112568811542089583575669787908089532582361954461677783851099925218078129638009
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
9.i2c_target_stress_all_with_rand_reset.81398492602541951838143693925500961512285323448088936184658817459690924939020
Line 609, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 3 failures:
15.i2c_tl_intg_err.83479808022057958011556741498761500430604554681437558644255652045437476967206
Line 323, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 41862845 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 41862845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_tl_intg_err.69154915404154870876555183152884681522599907420231216277069409488485192341514
Line 327, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 1239492543 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 1239492543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 3 failures:
32.i2c_target_stress_all_with_rand_reset.106168540309854726379421208975050020899714011982521048358020507422537636904897
Line 313, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4747162067 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (230 [0xe6] vs 8 [0x8])
UVM_INFO @ 4747162067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.i2c_target_stress_all_with_rand_reset.68054769118614998144768718789575615976504975957442990971677072433677300592782
Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1961760456 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (208 [0xd0] vs 209 [0xd1])
UVM_INFO @ 1961760456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 2 failures:
0.i2c_csr_bit_bash.10596549059996289674673394847250759760606590503931943638524032917124547823494
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 225583006 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 225583006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_csr_bit_bash.88033372455852909494355554126478141298143329411056270940878187840134636104724
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 2109149971 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 2109149971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
4.i2c_csr_bit_bash.32868649468612155545230822274870831306007058562835035179926941585913887352242
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2421367403 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2421367403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 1 failures:
9.i2c_tl_intg_err.37346849674656944981988683812725126582805067742148051184573381699098654821007
Line 396, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 466472471 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 466472471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
16.i2c_target_fifo_watermarks_tx.65489749998199224877292800974685165737694515875222058473623844056420208829046
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 722
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
16.i2c_same_csr_outstanding.45405635958219462476516512704670332084510537357641299315664115684938782318981
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 27638365 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 27638365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:752) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
38.i2c_target_stress_all_with_rand_reset.45295693775995849911509991893105772035482472945931003209415487703369216822341
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3644631466 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3644631466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---