32d52b8d41| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.915m | 28.455ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 57.820s | 3.312ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.780s | 29.382us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 63.894us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.600s | 2.500ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.440s | 81.055us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.520s | 113.589us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 63.894us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.440s | 81.055us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 10.660s | 270.673us | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 35.615m | 31.096ms | 41 | 50 | 82.00 |
| V2 | host_maxperf | i2c_host_perf | 23.242m | 26.958ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.740s | 75.293us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.781m | 5.499ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.757m | 3.726ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.190s | 618.022us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 26.720s | 513.179us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.400s | 249.324us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.710m | 3.240ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 45.060s | 1.118ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.024m | 2.513ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 29.602m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 11.230s | 9.138ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 26.343m | 43.722ms | 1 | 50 | 2.00 |
| V2 | target_maxperf | i2c_target_perf | 1.290s | 1.921ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.228m | 7.699ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.790s | 3.128ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 54.110s | 10.123ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.417m | 10.185ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 29.921m | 60.582ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.228m | 7.699ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 8.291m | 22.760ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.600s | 3.434ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 59.239m | 18.802ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.170s | 4.755ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.420s | 615.245us | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 7.080s | 1.506ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 6.330s | 1.056ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 29.740s | 2.503ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.680s | 15.541us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 16.821us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.510s | 66.952us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.510s | 66.952us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.780s | 29.382us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 63.894us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.440s | 81.055us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.240s | 501.627us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.780s | 29.382us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 63.894us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.440s | 81.055us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.240s | 501.627us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 1376 | 1542 | 89.23 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.500s | 259.809us | 17 | 20 | 85.00 |
| i2c_sec_cm | 0.970s | 319.699us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.500s | 259.809us | 17 | 20 | 85.00 |
| V2S | TOTAL | 22 | 25 | 88.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.703m | 20.606ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 15.311m | 104.708ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 25.730s | 2.592ms | 50 | 50 | 100.00 | |
| TOTAL | 1603 | 1872 | 85.63 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 48 | 33 | 25 | 52.08 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.06 | 96.60 | 90.21 | 97.67 | 69.64 | 93.62 | 98.44 | 91.26 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 98 failures:
0.i2c_target_perf.15287965521751082994790765195309073194966824639968344534956360278713876853273
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 152487146 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 152487146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.80759698918418540396926019270422190401377884692533916325191539839743952651229
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 8233240 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 8233240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
1.i2c_target_stress_all.14952176163599011567018211289517810648187418545179240237571522451982000884436
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 6588440860 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 6588440860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.113024152565685939625242010213698040783322069865161077890097653770830775477803
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 14245562653 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 14245562653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
1.i2c_target_stress_all_with_rand_reset.108228123998064487896426561966170631120286610928426354833623384302530205816683
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2982680057 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 2982680057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_all_with_rand_reset.72567750279184842272709673249484265573697249294205321675089253413653099686062
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 110210882 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 110210882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 54 failures:
0.i2c_host_stress_all_with_rand_reset.46440485237092799470675375544336674994211701162680991867598416831267835650258
Line 1302, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3131320019 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3131320019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.52341285605618586148027841825856871799845393429997945551409234206177436333328
Line 1362, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22211258544 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 22211258544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 43 more failures.
2.i2c_target_stress_all_with_rand_reset.82286864890148966040399537329184458448604089218878528844084382917114687830456
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1511313013 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1511313013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.692047473098631895934701938367640237429920835315355649778402702853392583217
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1390022531 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1390022531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 42 failures:
0.i2c_target_unexp_stop.105514972841160963329201252678246184543937371655082185764745330612075437132490
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 106818619 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 56 [0x38])
UVM_INFO @ 106818619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.104436798770782738242761068227879178391932986293844713192708091177437837309634
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 420578877 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 47 [0x2f])
UVM_INFO @ 420578877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
0.i2c_target_stress_all.50126508888591765754862102292730551190097092401020044914571702082597027471079
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 29921827353 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 81 [0x51])
UVM_INFO @ 29921827353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.75058952807171719985513174070830198193370382686810552330474665519509111064355
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 277805955 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 74 [0x4a])
UVM_INFO @ 277805955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
0.i2c_target_stress_all_with_rand_reset.64226516345345404703470898522268648757687390676615651112962760530928380273974
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4156935091 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 218 [0xda])
UVM_INFO @ 4156935091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.114384895763186975502628930031357866347886608710617947128458326906413323576389
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 44266552 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 155 [0x9b])
UVM_INFO @ 44266552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 31 failures:
1.i2c_target_unexp_stop.3939249068383263012710756264592996757022892027573762271257402302110700160052
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 281997624 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 281997624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_unexp_stop.18541359372278383526515370745095652821425236082433824227705353649426894682874
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 818033000 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 818033000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
3.i2c_target_stress_all_with_rand_reset.66849782656393708605768367263952423229668891575756744397422408724199826758748
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 184508236 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 184508236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.108567160338981711806555230503953348600380224790806227946262322131317051031069
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16912246 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 16912246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
4.i2c_target_stress_all.75119124714463838668007198481374618514085773278642645381626852869296460024548
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 25586882256 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 25586882256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_target_stress_all.106567176001723381051940030448327964626167705359035567476671742855994629329287
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 6308892648 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6308892648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
8.i2c_target_perf.56842096325690740587134560189252394653853383661736748386636486356998782926902
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_perf/latest/run.log
UVM_ERROR @ 53241196 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 53241196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
Test i2c_host_stress_all_with_rand_reset has 5 failures.
2.i2c_host_stress_all_with_rand_reset.69920320461389400719219060340814795577960342378796910342937927811096821233175
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:db483dc2-ed13-4e9e-a8e3-68f29b25fd34
12.i2c_host_stress_all_with_rand_reset.77231831528701617047813927638731258013535509705125271135814888433628405223123
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:75cf989d-1abb-40f1-8517-f6ed9b1d4246
... and 3 more failures.
Test i2c_target_unexp_stop has 3 failures.
7.i2c_target_unexp_stop.96164377890705269869259398912355158198267496408173236497733607544599885871742
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
Job ID: smart:559b9006-8d1a-4d96-97c3-4ba80119e59a
14.i2c_target_unexp_stop.30502693272254309833024231585500893477566312189660593698244944077230942763585
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
Job ID: smart:d9b42cb4-3059-4b4a-b7cf-7032d32ae858
... and 1 more failures.
Test i2c_target_stretch has 3 failures.
12.i2c_target_stretch.27838075542571602505703154506469670106970367881701229048057695021795369710468
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stretch/latest/run.log
Job ID: smart:d1eb7850-32af-4c29-8186-8ba9e5ffc728
21.i2c_target_stretch.31774806232259828211728759665771646149944075508138319228573194596387642387029
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stretch/latest/run.log
Job ID: smart:a2c80936-b4d5-474a-9529-115f89ceedbf
... and 1 more failures.
Test i2c_host_stress_all has 4 failures.
22.i2c_host_stress_all.89789694098818225246676348136203057797330033696134205084454672537412597815395
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
Job ID: smart:f20be4ee-5212-4d36-99cb-af383c6cdccb
31.i2c_host_stress_all.113549125550771759062297564855258225181899914297965330400179041792611123529007
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stress_all/latest/run.log
Job ID: smart:d26e14e8-c7f8-49e5-bce0-395145942ab8
... and 2 more failures.
Test i2c_target_stress_all has 1 failures.
40.i2c_target_stress_all.99615695000851171242587668829005812330038883711107244948668383151470813394464
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_stress_all/latest/run.log
Job ID: smart:ec52853b-ea1a-416f-9ee6-695d489e6d38
... and 1 more tests.
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 8 failures:
2.i2c_target_unexp_stop.12469758932631059933252807231841926452631091872866398406331398633938787223476
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 770080328 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 770080328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.104841325097006291015615640114281028625418715009808664032193021032436117359989
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 817129322 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 817129322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
33.i2c_target_stress_all.80052822221670075197016626186022634367539834068713416627900779157087887428915
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 751620870 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 751620870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_target_stress_all.9265723017788074490708659809545324974310004274884346835312995328592479256547
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 3847313302 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3847313302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 6 failures:
7.i2c_host_stress_all.10225606410585540450829794601183266946820343410299141601552034944181425455955
Line 7831, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 27477592803 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
17.i2c_host_stress_all.82519344968817998527193815922556927482954614733433563691878529319543257087218
Line 2339, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 5996621896 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
... and 3 more failures.
27.i2c_host_error_intr.10667863665096975617019415546114092491702095354034987761370937028298089193749
Line 848, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 417924366 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
4.i2c_target_unexp_stop.90884122869034257223186457613456469972755272936064059474801350765938380605464
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_unexp_stop.98615289658711368718357646979143921480904212620894770253244618823317899391885
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 3 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
5.i2c_target_stress_all_with_rand_reset.5145412991416598832306285709119758222348913047861881578480378306303021711517
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 209213186 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (7 [0x7] vs 4 [0x4])
UVM_INFO @ 209213186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
16.i2c_target_stress_all.25194274400826111365393546751610677003658868034465959182699854157043057862783
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 20710303861 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (10 [0xa] vs 8 [0x8])
UVM_INFO @ 20710303861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 1 failures.
41.i2c_target_unexp_stop.100919930415057036595793662266685620243740750075711226098518261700894091979985
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 282516855 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 1 [0x1])
UVM_INFO @ 282516855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 2 failures:
12.i2c_tl_intg_err.20249707460903244202678819724483573081066885949219418924095021008496884098709
Line 335, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 147826893 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 147826893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_tl_intg_err.65101725888403750063864848262630588804093250138344191245193801664747223754574
Line 311, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 64306726 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 64306726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 1 failures:
2.i2c_tl_intg_err.104399570469261036488192212003899312717717621660537238149200000455427499163216
Line 320, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 232199929 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 232199929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
2.i2c_same_csr_outstanding.20657348347252478919247555111950636812222403750406900373763718307935044279513
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 310085452 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 310085452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
7.i2c_target_stress_all_with_rand_reset.36982506923720662281082425230228384722595075172226883886514682936589941366804
Line 374, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 41114295772 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x9e794494) == 0x0
UVM_INFO @ 41114295772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
11.i2c_same_csr_outstanding.103152225197870159887393408634879178959804070605003197017436164866621019602939
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 55013231 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x812e6378 read out mismatch
UVM_INFO @ 55013231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---