302b24f3c6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.778m | 2.224ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 56.280s | 5.752ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.780s | 75.927us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.850s | 92.297us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.830s | 1.745ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.150s | 49.606us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.530s | 164.552us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.850s | 92.297us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.150s | 49.606us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 154 | 155 | 99.35 | |||
| V2 | host_error_intr | i2c_host_error_intr | 19.920s | 439.846us | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 38.001m | 23.328ms | 45 | 50 | 90.00 |
| V2 | host_maxperf | i2c_host_perf | 51.318m | 52.029ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.730s | 48.606us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.031m | 42.993ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.179m | 2.438ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.210s | 157.313us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 28.280s | 537.556us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.320s | 970.159us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.651m | 5.454ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 46.890s | 5.375ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.980m | 10.490ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 27.939m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 12.420s | 2.607ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 28.912m | 107.407ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 1.240s | 703.154us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.284m | 1.652ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.600s | 14.335ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 50.630s | 10.092ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.299m | 10.170ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 35.364m | 66.915ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.284m | 1.652ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 7.583m | 24.547ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.700s | 6.841ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 52.304m | 35.516ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.940s | 4.292ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.300s | 849.734us | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 7.260s | 1.515ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 6.660s | 1.126ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 30.270s | 2.629ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.680s | 16.005us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.790s | 18.055us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.630s | 443.900us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.630s | 443.900us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.780s | 75.927us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.850s | 92.297us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.150s | 49.606us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 55.653us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.780s | 75.927us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.850s | 92.297us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.150s | 49.606us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 55.653us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1375 | 1542 | 89.17 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.510s | 1.173ms | 19 | 20 | 95.00 |
| i2c_sec_cm | 0.970s | 224.159us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.510s | 1.173ms | 19 | 20 | 95.00 |
| V2S | TOTAL | 24 | 25 | 96.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.637m | 67.147ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 7.198m | 104.239ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 40.010s | 1.899ms | 50 | 50 | 100.00 | |
| TOTAL | 1603 | 1872 | 85.63 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 48 | 33 | 25 | 52.08 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.89 | 96.51 | 90.03 | 97.67 | 69.05 | 93.48 | 98.44 | 91.05 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 83 failures:
0.i2c_target_perf.40443876015735696237534132159417671289227469222097121504959591104705658327448
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 49068329 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 49068329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.114459595807884029326267565253471917252195795039502024390267609035137024491455
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 16740173 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 16740173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 46 more failures.
0.i2c_target_stress_all.31925196707844480248888265280999101712198931218209911691811089708341250798132
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 18410187364 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 18410187364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.105275424974418296724847326012059010747496562029182676166503573489891371335744
Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 12527532725 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 12527532725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
1.i2c_target_stress_all_with_rand_reset.31189273586803300842452229837672095140071442077497601901516210205960232863712
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 672546822 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 672546822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.52696629395975429810679049876614351809616684876755479462557005836275039923301
Line 291, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11794405774 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 11794405774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 51 failures:
0.i2c_host_stress_all_with_rand_reset.32767057145213102484062812811774530007635214700087729157153528034270295463099
Line 723, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4294612994 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4294612994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.15295665729812341504190344936610602263466542595521334074854934129657252701588
Line 3598, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25889043971 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 25889043971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 43 more failures.
8.i2c_target_stress_all_with_rand_reset.22819341965815049595651795108075806882786229038761011120703079651304905865017
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4817001267 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4817001267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stress_all_with_rand_reset.41364936820921043888364209446056369045238832712921126211928958558422603035948
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 495683649 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 495683649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 40 failures:
Test i2c_target_stress_all_with_rand_reset has 17 failures.
0.i2c_target_stress_all_with_rand_reset.114623805275141587247988885461682560412214150375859401766692674393803266149397
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 397138627 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 397138627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.27478600480968448547058785207390685790211356905790761777234813973740161001867
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 109476660 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 109476660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
Test i2c_target_unexp_stop has 14 failures.
3.i2c_target_unexp_stop.39157841482179584541379408056666627809998016141548439728178149908456741166572
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 37085066 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 37085066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.23102468324730120393791139640644359026693798387206862384202763549203957668468
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 101970402 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 101970402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Test i2c_target_perf has 2 failures.
3.i2c_target_perf.84673164104627292557509177042432921771189367607117732970575944800925149562442
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_perf/latest/run.log
UVM_ERROR @ 133217305 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 133217305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.i2c_target_perf.107526336094388108166186745157358201185700757923447595837357500715391155687302
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_perf/latest/run.log
UVM_ERROR @ 22095162 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 22095162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 7 failures.
11.i2c_target_stress_all.79232329732874308271334343112789891504700541356671760800332863512136257526529
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2248103229 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2248103229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all.57435220467234782043660002558287820626739934785674270036536830923446085506147
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 291971381 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 291971381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 39 failures:
1.i2c_target_unexp_stop.97032499093223946746571389602716928403968320381019030311632646599586191056621
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 70997603 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 190 [0xbe])
UVM_INFO @ 70997603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.52865565104859864955661557144037053808419890216114271618853327320450023006093
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 206254146 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 117 [0x75])
UVM_INFO @ 206254146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
3.i2c_target_stress_all_with_rand_reset.66170455262985555519894289321502909036051012755685364399661652496398223621349
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 804536707 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 176 [0xb0])
UVM_INFO @ 804536707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.73961689106500497404163236290884036683441587735073096709191564738968210585464
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 85801867 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 182 [0xb6])
UVM_INFO @ 85801867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
4.i2c_target_stress_all.12733772468328680183649790417965541891786454934565306837058838732790200968158
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 16192094972 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 223 [0xdf])
UVM_INFO @ 16192094972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all.83150086676999930075646869069394010111009886275298231510894025182968204194122
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 610951411 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 197 [0xc5])
UVM_INFO @ 610951411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
Test i2c_target_stretch has 7 failures.
0.i2c_target_stretch.35725629464061596781529012648162290239549851618774713652036127411035167357708
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
Job ID: smart:76ac3062-7fe2-4447-8ed3-8fc37982bbf9
7.i2c_target_stretch.67970237119399874244657243407826328096111001914898181658677747599586995033979
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
Job ID: smart:098c7ad9-926b-4fed-98c0-40c7cb1285af
... and 5 more failures.
Test i2c_host_perf has 1 failures.
2.i2c_host_perf.111541322036574917269111300545235254561494566992854875500701667319319577418974
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf/latest/run.log
Job ID: smart:847c5c9a-74ac-454c-88d4-375e4d6bb175
Test i2c_host_stress_all has 2 failures.
12.i2c_host_stress_all.41557101146103837656471583794534049344558790448614008708383192538720651270930
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
Job ID: smart:083be60a-3e3e-4cfb-bca2-32eae165c006
40.i2c_host_stress_all.29412581954723698510113254172461856904805448436327553870973308518408302215421
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_stress_all/latest/run.log
Job ID: smart:4305c058-573a-4f54-8e67-022d7267e096
Test i2c_target_unexp_stop has 2 failures.
13.i2c_target_unexp_stop.22693832910312699034825217456646658880299871452028839372302612811322742952828
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
Job ID: smart:0ca0de02-4a80-474a-9446-40788d75bf87
49.i2c_target_unexp_stop.80475981055881398908739890934914448977007545237646205347615106462640712113056
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_unexp_stop/latest/run.log
Job ID: smart:79c3b556-17ac-4c8d-ae2e-28accc7e419e
Test i2c_host_stress_all_with_rand_reset has 4 failures.
19.i2c_host_stress_all_with_rand_reset.87198844689502021774927862952389227067604927529308095673566675574453298901050
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:1f467105-3e6c-4e20-a269-43f638e873bc
28.i2c_host_stress_all_with_rand_reset.98874376822407679404257006053291963944978605355550784412878468896470974762266
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:90f7c67f-2c91-48db-9bbc-70a66590216a
... and 2 more failures.
... and 1 more tests.
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 8 failures:
7.i2c_target_stress_all_with_rand_reset.74008437341888043051331318777387432977607413704215124471929768947097414811409
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 280679969 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (30 [0x1e] vs 12 [0xc])
UVM_INFO @ 280679969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stress_all_with_rand_reset.15101913730706421056597865745739783236350501420596454726299765870334945497241
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 463751024 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 1 [0x1])
UVM_INFO @ 463751024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
14.i2c_target_stress_all.62878609740862718358443818655801972509820022685417054989462107773743871535497
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 85091315 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 2 [0x2])
UVM_INFO @ 85091315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_target_stress_all.4748038702473471074202482985743924389168256051815354641644375148766669584698
Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 5164193528 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 5 [0x5])
UVM_INFO @ 5164193528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
28.i2c_target_unexp_stop.109072624574667480625331932606395072336318528618435949232141502882849316585956
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 223151547 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 8 [0x8])
UVM_INFO @ 223151547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 7 failures:
0.i2c_target_unexp_stop.92491545088545862835463138840185941323960215281379585937856161215433580035267
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.23072938230378095843556225784030226502581359583896016709514609475083892609735
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
43.i2c_host_perf.32609114394314154314402305439333367911082827911489249477838075742918900461050
Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_host_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 6 failures:
4.i2c_target_unexp_stop.63581253807152802496463841755593893600797681912674077041800664704629869297069
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 2749296433 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2749296433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.98387608295639954925505198190552221623083481413948553469321811203878078001772
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 826184102 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 826184102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
42.i2c_target_stress_all.54997994230204121539959961137965664950883619055684369979146319810465501028542
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 774531621 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 774531621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred! has 5 failures:
1.i2c_target_stress_all.24797040200170869804088223355543295197956437748320565600108816615276799386688
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 121392131760 ps: (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 121392131760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_target_stress_all.10420169007971848019390769744104164565695545043321829115006848896342556917811
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 100762239271 ps: (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100762239271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 5 failures:
8.i2c_host_stress_all.93001620542672634014013130458033286947194337269144774033338708881702198547273
Line 1594, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 21850865284 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
10.i2c_host_stress_all.6871909679464344656850605707382723855579378397745148795701698289418220375586
Line 6502, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 6744320284 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
... and 1 more failures.
16.i2c_host_error_intr.71380295534721059810018522858426557937314925510410996889499963577551122420681
Line 286, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 91344465 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
41.i2c_host_error_intr.81983212049138785859232871824274206164743094959037638940332899531343929169824
Line 616, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 171772710 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
2.i2c_same_csr_outstanding.3368344427070757627729022388051539924328236731507240640193051353798207682378
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 176009932 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0xe0d54578 read out mismatch
UVM_INFO @ 176009932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
3.i2c_csr_bit_bash.69889530106683405325051779831566155603824660283942342185750655367554276309361
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 79988100 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 79988100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:752) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
10.i2c_target_stress_all_with_rand_reset.419681268447524296377046424624674995959002740446344901986231854024957967820
Line 309, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29884150633 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 29884150633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
12.i2c_host_stress_all_with_rand_reset.38689303968398245878974414402513956648193049038958298797049692622732690955308
Line 2657, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9107395446 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (6 [0x6] vs 3 [0x3])
UVM_INFO @ 9107395446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 1 failures:
18.i2c_tl_intg_err.47180940388561535800936441082274314650169824916251741640071940614961839436631
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 6776304 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 6776304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 1 failures:
23.i2c_target_unexp_stop.9720117872153166812963687394945620677734175421822354559951183763912583433920
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 11591224135 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 11591224135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:776) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
28.i2c_target_stress_all_with_rand_reset.29145381141499858583354164194652937436947519959515008342690760451194268839088
Line 397, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 104239019025 ps: (i2c_scoreboard.sv:776) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (221 [0xdd] vs 220 [0xdc])
UVM_INFO @ 104239019025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
48.i2c_target_stress_all_with_rand_reset.96078847760198708341876928209986153889911595689436510880566076928714928276013
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10717168191 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x2374a094) == 0x0
UVM_INFO @ 10717168191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---