I2C Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 0 50 0.00
V1 target_smoke i2c_target_smoke 0 50 0.00
V1 csr_hw_reset i2c_csr_hw_reset 0.800s 30.400us 5 5 100.00
V1 csr_rw i2c_csr_rw 1.740s 545.641us 20 20 100.00
V1 csr_bit_bash i2c_csr_bit_bash 6.150s 662.577us 3 5 60.00
V1 csr_aliasing i2c_csr_aliasing 2.240s 142.326us 5 5 100.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 1.610s 32.692us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 1.740s 545.641us 20 20 100.00
i2c_csr_aliasing 2.240s 142.326us 5 5 100.00
V1 TOTAL 53 155 34.19
V2 host_error_intr i2c_host_error_intr 0 50 0.00
V2 host_stress_all i2c_host_stress_all 0 50 0.00
V2 host_maxperf i2c_host_perf 0 50 0.00
V2 host_override i2c_host_override 0 50 0.00
V2 host_fifo_watermark i2c_host_fifo_watermark 0 50 0.00
V2 host_fifo_overflow i2c_host_fifo_overflow 0 50 0.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 0 50 0.00
i2c_host_fifo_fmt_empty 0 50 0.00
i2c_host_fifo_reset_rx 0 50 0.00
V2 host_fifo_full i2c_host_fifo_full 0 50 0.00
V2 host_timeout i2c_host_stretch_timeout 0 50 0.00
V2 host_rx_oversample i2c_host_rx_oversample 0 0 --
V2 i2c_host_mode_toggle i2c_host_mode_toggle 0 50 0.00
V2 target_error_intr i2c_target_unexp_stop 0 50 0.00
V2 target_glitch i2c_target_glitch 0 2 0.00
V2 target_stress_all i2c_target_stress_all 0 50 0.00
V2 target_maxperf i2c_target_perf 0 50 0.00
V2 target_fifo_empty i2c_target_stress_rd 0 50 0.00
i2c_target_intr_smoke 0 50 0.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 0 50 0.00
i2c_target_fifo_reset_tx 0 50 0.00
V2 target_fifo_full i2c_target_stress_wr 0 50 0.00
i2c_target_stress_rd 0 50 0.00
i2c_target_intr_stress_wr 0 50 0.00
V2 target_timeout i2c_target_timeout 0 50 0.00
V2 target_clock_stretch i2c_target_stretch 0 50 0.00
V2 bad_address i2c_target_bad_addr 0 50 0.00
V2 target_mode_glitch i2c_target_hrst 0 50 0.00
V2 target_fifo_watermark i2c_target_fifo_watermarks_acq 0 50 0.00
i2c_target_fifo_watermarks_tx 0 50 0.00
V2 host_mode_config_perf host_mode_config_perf 0 0 --
V2 host_mode_clock_stretching host_mode_clock_stretching 0 0 --
V2 target_mode_tx_stretch_ctrl i2c_target_tx_stretch_ctrl 0 50 0.00
V2 target_mode_nack_generation target_mode_nack_generation 0 0 --
V2 host_mode_halt_on_nak host_mode_halt_on_nak 0 0 --
V2 target_mode_n_byte_ack_control target_mode_n_byte_ack_control 0 0 --
V2 target_mode_bus_timeout target_mode_bus_timeout 0 0 --
V2 controller_mode_bus_timeout controller_mode_bus_timeout 0 0 --
V2 controller_mode_bus_idle_delay controller_mode_bus_idle_delay 0 0 --
V2 loopback_test loopback_test 0 0 --
V2 multi_controller_clock_synchronization multi_controller_clock_synchronization 0 0 --
V2 multi_controller_arbitration_lost_interference multi_controller_arbitration_lost_interference 0 0 --
V2 multi_controller_arbitration_lost multi_controller_arbitration_lost 0 0 --
V2 target_mode_arbitration_lost_interference target_mode_arbitration_lost_interference 0 0 --
V2 target_mode_arbitration_lost target_mode_arbitration_lost 0 0 --
V2 alert_test i2c_alert_test 0 50 0.00
V2 intr_test i2c_intr_test 0.740s 21.946us 50 50 100.00
V2 tl_d_oob_addr_access i2c_tl_errors 2.770s 134.035us 20 20 100.00
V2 tl_d_illegal_access i2c_tl_errors 2.770s 134.035us 20 20 100.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 0.800s 30.400us 5 5 100.00
i2c_csr_rw 1.740s 545.641us 20 20 100.00
i2c_csr_aliasing 2.240s 142.326us 5 5 100.00
i2c_same_csr_outstanding 1.300s 64.475us 19 20 95.00
V2 tl_d_partial_access i2c_csr_hw_reset 0.800s 30.400us 5 5 100.00
i2c_csr_rw 1.740s 545.641us 20 20 100.00
i2c_csr_aliasing 2.240s 142.326us 5 5 100.00
i2c_same_csr_outstanding 1.300s 64.475us 19 20 95.00
V2 TOTAL 89 1542 5.77
V2S tl_intg_err i2c_tl_intg_err 2.620s 1.345ms 17 20 85.00
i2c_sec_cm 0 5 0.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 2.620s 1.345ms 17 20 85.00
V2S TOTAL 17 25 68.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 0 50 0.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 0 50 0.00
V3 target_loopback 0 0 --
V3 TOTAL 0 100 0.00
Unmapped tests i2c_host_may_nack 0 50 0.00
TOTAL 159 1872 8.49

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 7 7 4 57.14
V2 48 33 2 4.17
V2S 2 2 0 0.00
V3 3 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
52.81 40.66 40.76 91.14 0.00 42.98 99.68 54.42

Failure Buckets

Past Results