a8c9c17a8c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.096m | 9.106ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 1.037m | 6.190ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.880s | 164.317us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.880s | 20.516us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.360s | 1.129ms | 3 | 5 | 60.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.350s | 600.686us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.450s | 38.887us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.880s | 20.516us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.350s | 600.686us | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 152 | 155 | 98.06 | |||
| V2 | host_error_intr | i2c_host_error_intr | 8.950s | 846.543us | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 45.121m | 155.477ms | 47 | 50 | 94.00 |
| V2 | host_maxperf | i2c_host_perf | 19.723m | 31.483ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.750s | 15.603us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.583m | 4.983ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.536m | 10.773ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.190s | 610.554us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 28.800s | 8.674ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 14.070s | 234.197us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.966m | 5.881ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 43.600s | 912.059us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.304m | 12.616ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 8.250m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 12.420s | 14.492ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 32.282m | 100.135ms | 2 | 50 | 4.00 |
| V2 | target_maxperf | i2c_target_perf | 1.110s | 173.366us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.468m | 3.654ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.000s | 12.013ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 55.650s | 10.104ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.285m | 10.126ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 54.565m | 71.185ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.468m | 3.654ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 12.671m | 26.242ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.830s | 6.656ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 46.903m | 15.395ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.360s | 1.011ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.370s | 554.627us | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 7.220s | 1.463ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 6.500s | 1.032ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 29.490s | 2.385ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.710s | 139.672us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 19.288us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.170s | 295.742us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.170s | 295.742us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.880s | 164.317us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.880s | 20.516us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.350s | 600.686us | 4 | 5 | 80.00 | ||
| i2c_same_csr_outstanding | 1.320s | 186.857us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.880s | 164.317us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.880s | 20.516us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.350s | 600.686us | 4 | 5 | 80.00 | ||
| i2c_same_csr_outstanding | 1.320s | 186.857us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 1380 | 1542 | 89.49 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.630s | 136.146us | 18 | 20 | 90.00 |
| i2c_sec_cm | 1.010s | 149.787us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.630s | 136.146us | 18 | 20 | 90.00 |
| V2S | TOTAL | 23 | 25 | 92.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.068m | 46.179ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 16.674m | 90.114ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 31.930s | 738.301us | 50 | 50 | 100.00 | |
| TOTAL | 1605 | 1872 | 85.74 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 5 | 71.43 |
| V2 | 48 | 33 | 25 | 52.08 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.79 | 96.51 | 89.76 | 97.22 | 69.05 | 93.48 | 98.44 | 91.05 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 98 failures:
0.i2c_target_perf.63320240677004919184299415566892582560257761764205057222476058078530709283840
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 100096900 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 100096900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.88511289206803393400661273400711181532761134000449571166288614837364172390692
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 18155123 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 18155123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.i2c_target_stress_all_with_rand_reset.61888851160162252708774377417067463699909401242128931998266063137660318803499
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36458997 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 36458997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.113415261484214655315065995009592208741876070446192730007137511011394974197922
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 114768427 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 114768427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
1.i2c_target_stress_all.105957210101269321279001340562722648039536020315706801177190738202452422438651
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 36754211643 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 36754211643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.36814319348050312349777886033071962611556894781641440800945940940788274478221
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 53021753 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 53021753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 56 failures:
0.i2c_host_stress_all_with_rand_reset.49136974632851641399598463284588910144264391539389683780445164639109369418407
Line 5712, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8039615210 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8039615210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.68861354689006799716706759097974071499079625671600700750329118562976216177462
Line 1200, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3554372617 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3554372617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 45 more failures.
1.i2c_target_stress_all_with_rand_reset.54884125195990670186804395985342649387104366521505097924549156665937060981018
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4352928335 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4352928335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.75216863087883223409293548727705391301991153108257642105502676520560321857713
Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22200750789 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 22200750789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 44 failures:
0.i2c_target_unexp_stop.89782459433295980767366036080766371592476898212354927423125235026351954163320
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 263245466 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 232 [0xe8])
UVM_INFO @ 263245466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.900053213213832800626884122631660357763204328309748099508044235209707377015
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 225691814 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 220 [0xdc])
UVM_INFO @ 225691814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
6.i2c_target_stress_all_with_rand_reset.33585737635692558294366258692995163096635609757055114068706476497122111753229
Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2452638612 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 19 [0x13])
UVM_INFO @ 2452638612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.82892634308495518193670211469879163825495713163981729593816914989503761915035
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18912264076 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 138 [0x8a])
UVM_INFO @ 18912264076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
17.i2c_target_stress_all.32724776960574639099479982310670089563783924762289666681319932433138345901277
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 53340966 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 131 [0x83])
UVM_INFO @ 53340966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stress_all.96641431433422611558194066998737214769265985204890227629752386414995162821725
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 8696173625 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 226 [0xe2])
UVM_INFO @ 8696173625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 25 failures:
5.i2c_target_unexp_stop.110728549156957737241080529553971798216261790327220432755319367327067656354913
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 114137699 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 114137699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.30878488191692289296247066957614585379813386456927676964199839626186521234186
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 309723923 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 309723923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
6.i2c_target_stress_all.74360203600963905342004840824597072713731944915225083857837109234480812549021
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 7073483433 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 7073483433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all.67974392801698249722792351611272556141063710683731907201230159525691711138092
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 561560022 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 561560022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
18.i2c_target_stress_all_with_rand_reset.17092886290627933568977569266174584274351970557524886596185089311907132637173
Line 682, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26245090032 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 26245090032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_stress_all_with_rand_reset.114277117405537648880970686391655922736461409100596291874538744606996958218562
Line 315, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5982704131 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5982704131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
Test i2c_target_stretch has 6 failures.
6.i2c_target_stretch.45797667877819719723881787735968905818011838387264487626111223004714299949318
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
Job ID: smart:fa14ec58-b85b-4e4e-868b-2ebb977536f4
12.i2c_target_stretch.85061742559757947008609836756402860278541555411842604660164495512104171046697
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stretch/latest/run.log
Job ID: smart:bac93168-45a0-4759-9dfd-a5145ca57833
... and 4 more failures.
Test i2c_host_stress_all_with_rand_reset has 1 failures.
7.i2c_host_stress_all_with_rand_reset.23961540594238330059691603962585268320653633607351141092120587738996135701819
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:4e14a9d8-b818-4196-806a-fe0cdd2a5f8b
Test i2c_target_unexp_stop has 5 failures.
16.i2c_target_unexp_stop.62036790871735945567772599291502767270399984939019254306900540179668594804802
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log
Job ID: smart:4f05a508-ba72-49e6-87da-de03ca242831
18.i2c_target_unexp_stop.85426731904157174343402864008096882709314664882023181065703335914049826605024
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_unexp_stop/latest/run.log
Job ID: smart:f7972271-cc8a-4a53-8174-48906f20096d
... and 3 more failures.
Test i2c_host_stress_all has 2 failures.
20.i2c_host_stress_all.6373733867163150208046640496580947857579864169332173687607046790680539520476
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log
Job ID: smart:5af3e954-865b-408d-a56e-4930f6d0d030
27.i2c_host_stress_all.83955182765341200584604972967257448660033310456743229757017978534227586462168
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
Job ID: smart:df0da456-80b4-4ec4-870f-e9c2894669ad
Test i2c_target_stress_all has 1 failures.
33.i2c_target_stress_all.53304262813968180611995521041241575355063083877018130411026376010641763215750
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all/latest/run.log
Job ID: smart:d506eb38-4268-43ee-ad07-bed56347310b
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 8 failures:
0.i2c_target_stress_all.25825841542934319735157760937029895015871876462094904345170196283100960957760
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 724540339 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 724540339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_all.113194505134927764457524449785128258680376027846605078092697496298507770945418
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1497636511 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1497636511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
17.i2c_target_unexp_stop.110804982982036933725358857778828286249301441954111169381624205288687706262738
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1523334236 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1523334236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_target_unexp_stop.3053934162608469935147137733615117598730863284599388555616765637516673488270
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 720257633 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 720257633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 4 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
6.i2c_host_stress_all_with_rand_reset.109970288177264199609401027159129672143011570957352723962249141385217022491425
Line 9869, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 47001328710 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
Test i2c_host_error_intr has 2 failures.
18.i2c_host_error_intr.94380266806949356870846983922282595957582848111214118209321190150068587993294
Line 1032, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 176639762 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
49.i2c_host_error_intr.109295056448053242473487650336003270980289205483651848600550735352190215345245
Line 756, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 449843352 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
Test i2c_host_stress_all has 1 failures.
45.i2c_host_stress_all.113752035655632697470684808659380128349248062299160935115810452431874858191850
Line 9874, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 25526341685 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 3 failures:
Test i2c_csr_aliasing has 1 failures.
2.i2c_csr_aliasing.89329000068795409557170542800212570710597104760822723211117237606872760317089
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_aliasing/latest/run.log
UVM_ERROR @ 33600764 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 33600764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_tl_intg_err has 2 failures.
12.i2c_tl_intg_err.24388696055454361442419309812423371540490005175408881969516305239636903795442
Line 333, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 69903529 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 69903529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_tl_intg_err.94337111079655835092504939091900402899604311773561828031253252594217254180161
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 12534016 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 12534016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred! has 2 failures:
2.i2c_target_stress_all.13665719771442808850700554622913918552260293597592852776110544507586766580019
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 109627595538 ps: (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 109627595538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.i2c_target_stress_all.91266375295429064135085537473771017698085013589288648471490541907384365680219
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 100134841464 ps: (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100134841464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 2 failures:
4.i2c_target_stress_all_with_rand_reset.2106400518627257092410436291851729884756562396267546927806184440567853199797
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10200788769 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x81b4e614) == 0x0
UVM_INFO @ 10200788769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.i2c_target_stress_all_with_rand_reset.1202160125652279774840701778388231750792704380609894979336800487489045214711
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10136077178 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xdeeeee94) == 0x0
UVM_INFO @ 10136077178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:
10.i2c_same_csr_outstanding.89896508549682777977397770244163406984109571172615306628257326251440856062141
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 24319814 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0xdc3faef8 read out mismatch
UVM_INFO @ 24319814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_same_csr_outstanding.91025819880685873189428340539627774596496864294431804943071384726310398641062
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 14653792 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x583f0ff8 read out mismatch
UVM_INFO @ 14653792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 2 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
13.i2c_target_stress_all_with_rand_reset.96122727986141931759404217180919709339517568054228575796050991799380132885010
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 15998798882 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 15998798882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 1 failures.
49.i2c_target_unexp_stop.148204424445391398280961455008703665818541624034642435841201061630511928178
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 10780774096 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10780774096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
1.i2c_csr_bit_bash.47013280068012575939760611824607959616952433948675360087788370213334875466120
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1090806693 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1090806693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
3.i2c_csr_bit_bash.70699835386102981958162781311611578102627930218252600915721036151409548353108
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 362635766 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 362635766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
6.i2c_target_unexp_stop.113035041987490010486103033218889700962604512986377865781237992842201230163576
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 1 failures:
29.i2c_target_stress_all.103317283664683367311010071240549886910637450104773887377306917942923714341762
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 44251270 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (2 [0x2] vs 1 [0x1])
UVM_INFO @ 44251270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
31.i2c_host_stress_all_with_rand_reset.103933555960097623230841873537076750191060898393064564079419411953360348444077
Line 14468, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 45896639526 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
UVM_INFO @ 45896639526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*) == * has 1 failures:
35.i2c_host_perf.83535665322160265172648183143133627463285349739394630632526399422099650300805
Line 524, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_perf/latest/run.log
UVM_FATAL @ 13727765084 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0x36150994) == 0x0
UVM_INFO @ 13727765084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---